Stereo, Low Power, 96 kHz, 24-Bit
Audio Codec with Integrated PLL
ADAU1361
FEATURES
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
6 analog input pins, configurable for single-ended or
differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo,
1 mono headphone output driver
PLL supporting input clocks from 8 MHz to 27 MHz
Analog automatic level control (ALC)
Microphone bias reference voltage
Analog and digital I/O: 1.8 V to 3.65 V
I
2
C and SPI control interfaces
Digital audio serial data I/O: stereo and time-division
multiplexing (TDM) modes
Software-controllable clickless mute
Software power-down
32-lead, 5 mm × 5 mm LFCSP
−40°C to +85°C operating temperature range
GENERAL DESCRIPTION
The ADAU1361 is a low power, stereo audio codec that supports
stereo 48 kHz record and playback at 14 mW from a 1.8 V analog
supply. The stereo audio ADCs and DACs support sample rates
from 8 kHz to 96 kHz as well as a digital volume control. The
ADAU1361 is ideal for battery-powered audio and telephony
applications.
The record path includes an integrated microphone bias circuit
and six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1361 includes a stereo digital microphone input.
The ADAU1361 includes five high power output drivers (two
differential and three single-ended), supporting stereo head-
phones, an earpiece, or other output transducer. AC-coupled
or capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.
The serial control bus supports the I
2
C and SPI protocols. The
serial audio bus is programmable for I
2
S, left-/right-justified,
and TDM modes. A programmable PLL supports flexible clock
generation for all standard integer rates and fractional master
clocks from 8 MHz to 27 MHz.
APPLICATIONS
Smartphones/multimedia phones
Digital still cameras/digital video cameras
Portable media players/portable audio players
Phone accessories products
DVDDOUT
FUNCTIONAL BLOCK DIAGRAM
IOVDD
DGND
AGND
AGND
AVDD
AVDD
CM
JACKDET/MICIN
HP JACK
DETECTION
REGULATOR
ADAU1361
LAUX
LINP
ADC
LINN
RINP
RINN
RAUX
INPUT
MIXERS
ALC
ADC
ADC
DAC
DIGITAL DIGITAL
FILTERS FILTERS
DAC
DAC
LOUTP
LOUTN
LHP
OUTPUT
MIXERS
MONOOUT
RHP
ROUTP
ROUTN
MICBIAS
MICROPHONE
BIAS
PLL
SERIAL DATA
INPUT/OUTPUT PORTS
I
2
C/SPI
CONTROL PORT
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
07679-001
MCLK ADC_SDATA
LRCLK
BCLK
DAC_SDATA ADDR0/ ADDR1/ SCL/ SDA/
CLATCH CDATA CCLK COUT
ADAU1361
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance Specifications ........................................... 4
Power Supply Specifications........................................................ 7
Typical Current Consumption.................................................... 8
Typical Power Management Measurements ............................. 9
Digital Filters............................................................................... 10
Digital Input/Output Specifications......................................... 10
Digital Timing Specifications ................................................... 11
Digital Timing Diagrams........................................................... 12
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 17
System Block Diagrams ................................................................. 20
Theory of Operation ...................................................................... 23
Startup, Initialization, and Power ................................................. 24
Power-Up Sequence ................................................................... 24
Power Reduction Modes............................................................ 24
Digital Power Supply.................................................................. 24
Input/Output Power Supply...................................................... 24
Clock Generation and Management........................................ 24
Clocking and Sampling Rates ....................................................... 26
Core Clock................................................................................... 26
Sampling Rates............................................................................ 26
PLL ............................................................................................... 27
Record Signal Path ......................................................................... 29
Input Signal Paths....................................................................... 29
Analog-to-Digital Converters................................................... 31
Automatic Level Control (ALC)................................................... 32
ALC Parameters.......................................................................... 32
Noise Gate Function .................................................................. 33
Playback Signal Path ...................................................................... 35
Output Signal Paths ................................................................... 35
Headphone Output .................................................................... 36
Pop-and-Click Suppression ...................................................... 37
Line Outputs ............................................................................... 37
Control Ports................................................................................... 38
Burst Mode Writing and Reading ............................................ 38
I
2
C Port ........................................................................................ 38
SPI Port ........................................................................................ 41
Serial Data Input/Output Ports .................................................... 42
Applications Information .............................................................. 44
Power Supply Bypass Capacitors.............................................. 44
GSM Noise Filter ........................................................................ 44
Grounding ................................................................................... 44
Exposed Pad PCB Design ......................................................... 44
Control Registers ............................................................................ 45
Control Register Details ............................................................ 46
Outline Dimensions ....................................................................... 79
Ordering Guide .......................................................................... 79
Rev. C | Page 2 of 80
ADAU1361
REVISION HISTORY
9/10—Rev. B to Rev. C
Changes to Figure 1...........................................................................1
5/10—Rev. A to Rev. B
Changes to Burst Mode Writing and Reading Section ..............38
Changes to Table 26 ........................................................................45
Change to Table 43..........................................................................58
Added R67: Dejitter Control, 16,438 (0x4036) Section .............73
12/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Changes to General Description Section .......................................1
Changes to Table 1 ............................................................................6
Change to Table 5 ............................................................................10
Changes to Figure 6.........................................................................13
Changes to Table 10 ........................................................................15
Changes to Captions of Figure 15, Figure 16, Figure 18,
and Figure 19 ...................................................................................18
Changes to Captions of Figure 21 and Figure 24 ........................19
Added Figure 22; Renumbered Sequentially ...............................19
Change to Figure 25 ........................................................................20
Change to Figure 26 ........................................................................21
Change to Figure 27 ........................................................................22
Change to Theory of Operation Section ......................................23
Changes to Power Reduction Modes Section and
Case 1: PLL Is Bypassed Section ...................................................24
Changes to PLL Lock Acquisition Section...................................25
Changes to Core Clock Section.....................................................26
Changes to Input Signal Paths Section and Figure 31................29
Changes to Figure 32 and Figure 33 .............................................30
Changes to ADC Full-Scale Level Section ...................................31
Change to Automatic Level Control (ALC) Section...................32
Changes to Output Signal Paths Section......................................35
Changes to Headphone Output Section.......................................36
Changes to Jack Detection Section, Pop-and-Click
Suppression Section, and Line Outputs Section .........................37
Changes to Control Ports Section and I
2
C Port Section............38
Added Burst Mode Writing and Reading Section ......................38
Changes to SPI Port Section ..........................................................41
Changes to Serial Data Input/Output Ports Section, Table 24,
and Table 25 .....................................................................................42
Added Figure 56 ..............................................................................42
Changes to Figure 60 and Figure 61 .............................................43
Changes to Table 26 ........................................................................45
Changes to R2: Digital Microphone/Jack Detection Control,
16,392 (0x4008) Section and Table 29..........................................47
Changes to Table 35 ........................................................................52
Changes to Table 36 ........................................................................53
Changes to R15: Serial Port Control 0, 16,405 (0x4015)
Section and Table 42 .......................................................................57
Change to Table 43..........................................................................58
Changes to Table 44, R18: Converter Control 1, 16,408
(0x4018) Section, and Table 45 .....................................................59
Changes to Table 53, R27: Playback L/R Mixer Right (Mixer 6)
Line Output Control, 16,417 (0x4021) Section, and Table 54...65
Changes to Table 55, R29: Playback Headphone Left Volume
Control, 16,419 (0x4023) Section, and Table 56 .........................66
Changes to R42: Jack Detect Pin Control, 16,433 (0x4031)
Section and Table 69 .......................................................................73
1/09—Revision 0: Initial Version
Rev. C | Page 3 of 80
ADAU1361
SPECIFICATIONS
Supply voltage (AVDD) = 3.3 V, T
A
= 25°C, master clock = 12.288 MHz (48 kHz f
S
, 256 × f
S
mode), input sample rate = 48 kHz, measurement
bandwidth = 20 Hz to 20 kHz, word width = 24 bits, C
LOAD
(digital output) = 20 pF, I
LOAD
(digital output) = 2 mA, V
IH
= 2 V, V
IL
= 0.8 V,
unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase
deviation specifications.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient).
Table 1.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
Single-Ended Line Input
Test Conditions/Comments
ADC performance excludes mixers
and PGA
All ADCs
Min
Typ
Max
Unit
24
0.375
95
83
21
10.5
84.5
53
2
105
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
94
99
91
96
−88
−90
94
99
91
96
3
−12
−87
0.005
0
−12
68
+6
Bits
dB
dB
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
%
dB
dB
dB
PGA Inverting Inputs
PGA Noninverting Inputs
SINGLE-ENDED LINE INPUT
Full-Scale Input Voltage (0 dB)
−12 dB gain
0 dB gain
6 dB gain
−12 dB gain
0 dB gain
35.25 dB gain
All gains
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Gain per Step
Total Gain Range
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
CM capacitor = 20 μF
100 mV p-p @ 217 Hz
100 mV p-p @ 1 kHz
65
67
Rev. C | Page 4 of 80
ADAU1361
Parameter
PSEUDO-DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Test Conditions/Comments
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
PGA gain
Min
Typ
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
92
98
90
95
−88
−89
92
98
90
95
0.75
−12
20
−87
0.005
0
−14
83
65
65
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
92
98
90
95
−70
−78
92
98
90
95
0.75
−12
20
−87
0.005
0
−14
+35.25
+35.25
Max
Unit
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
%
dB
dB
dB
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
%
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
FULL DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Differential PGA inputs
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
PGA gain
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Rev. C | Page 5 of 80
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