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PI7C8154BNA

Description
PCI Bus Controller, CMOS, PBGA304, PLASTIC, BGA-304
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size824KB,112 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet Parametric View All

PI7C8154BNA Overview

PCI Bus Controller, CMOS, PBGA304, PLASTIC, BGA-304

PI7C8154BNA Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging codeBGA
package instructionBGA, BGA304,23X23,50
Contacts304
Reach Compliance Codecompliant
ECCN codeEAR99
Address bus width32
maximum clock frequency66 MHz
External data bus width32
JESD-30 codeS-PBGA-B304
JESD-609 codee0
length31 mm
Humidity sensitivity level3
Number of terminals304
Maximum operating temperature85 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA304,23X23,50
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
Maximum seat height2.53 mm
Maximum slew rate417 mA
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width31 mm
uPs/uCs/peripheral integrated circuit typeBUS CONTROLLER, PCI

PI7C8154BNA Preview

PI7C8154B
Asynchronous 2-Port
PCI-to-PCI Bridge
REVISION 1.00
3545 North 1
st
Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Email:
solutions@pericom.com
Internet:
http://www.pericom.com
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a
specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1)
Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the
right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to
supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other
than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described
herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
2)
All other trademarks are of their respective companies.
Page 2 of 112
JULY 2004 REVISION 1.00
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
REVISION HISTORY
Date
07/10/04
07/26/04
Revision Number
0.03
1.00
Description
Initial release of preliminary specification
Initial release of specification to the web
Updated Power Dissipation in section 17.9
Updated T
DELAY
in sections 17.4 and 17.5
Revised V
IH
parameter in section 17.2
Page 3 of 112
JULY 2004 REVISION 1.00
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
This page intentionally left blank.
Page 4 of 112
JULY 2004 REVISION 1.00
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
TABLE OF CONTENTS
LIST OF TABLES...............................................................................................................................................10
LIST OF FIGURES.............................................................................................................................................10
INTRODUCTION ...............................................................................................................................................11
1
SIGNAL DEFINITIONS ...........................................................................................................................12
1.1
SIGNAL TYPES.................................................................................................................................12
1.2
SIGNALS ...........................................................................................................................................12
1.2.1
PRIMARY BUS INTERFACE SIGNALS ........................................................................................12
1.2.2
PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION ...................................................14
1.2.3
SECONDARY BUS INTERFACE SIGNALS ..................................................................................15
1.2.4
SECONDARY BUS INTERFACE SIGNALS – 64-EXTENSTION..................................................17
1.2.5
CLOCK SIGNALS..........................................................................................................................17
1.2.6
MISCELLANEOUS SIGNALS........................................................................................................18
1.2.7
GENERAL PURPOSE I/O INTERFACE SIGNALS.......................................................................19
1.2.8
JTAG BOUNDARY SCAN SIGNALS .............................................................................................19
1.2.9
POWER AND GROUND ...............................................................................................................19
1.3
PIN LIST ............................................................................................................................................20
2
SIGNAL DEFINITIONS ...........................................................................................................................23
2.1
2.2
2.3
2.4
2.5
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.9
2.9.1
2.9.2
2.9.3
2.9.4
2.9.5
TYPES OF TRANSACTIONS ...........................................................................................................23
SINGLE ADDRESS PHASE..............................................................................................................24
DUAL ADDRESS PHASE.................................................................................................................24
DEVICE SELECT (DEVSEL#) GENERATION ...............................................................................24
DATA PHASE....................................................................................................................................24
WRITE TRANSACTIONS ................................................................................................................25
MEMORY WRITE TRANSACTIONS .............................................................................................25
MEMORY WRITE AND INVALIDATE..........................................................................................26
DELAYED WRITE TRANSACTIONS ............................................................................................26
WRITE TRANSACTION ADDRESS BOUNDARIES......................................................................27
BUFFERING MULTIPLE WRITE TRANSACTIONS ....................................................................27
FAST BACK-TO-BACK TRANSACTIONS ....................................................................................28
READ TRANSACTIONS ..................................................................................................................28
PREFETCHABLE READ TRANSACTIONS ..................................................................................28
NON-PREFETCHABLE READ TRANSACTIONS.........................................................................28
READ PREFETCH ADDRESS BOUNDARIES .............................................................................29
DELAYED READ REQUESTS.......................................................................................................29
DELAYED READ COMPLETION ON TARGET BUS ..................................................................30
DELAYED READ COMPLETION ON INITIATOR BUS ..............................................................30
FAST BACK-TO-BACK TRANSACTIONS ....................................................................................31
CONFIGURATION TRANSACTIONS ............................................................................................31
TYPE 0 ACCESS TO PI7C8154A ..................................................................................................32
TYPE 1 TO TYPE 0 CONFIGURATION .......................................................................................32
TYPE 1 TO TYPE 1 FORWARDING .............................................................................................34
SPECIAL CYCLES.........................................................................................................................34
64-BIT OPERATION .........................................................................................................................35
64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154B .............................................35
64-BIT TRANSACTIONS – ADDRESS PHASE .............................................................................35
64-BIT TRANSACTIONS – DATA PHASE ....................................................................................36
64-BIT TRANSACTIONS – RECEIVED BY PI7C8154B ...............................................................36
64-BIT TRANSACTIONS – SUPPORT DURING RESET..............................................................37
Page 5 of 112
JULY 2004 REVISION 1.00
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