PI7C8152
2-PORT PCI-to-PCI BRIDGE
DATA BRIEF
PI7C8152
2-Port PCI-to-PCI Bridge, 32-bit / 66 MHz or 33 MHz
PRODUCT FEATURES
·
32-Bit / 66 MHz or 33 MHz Primary and
Secondary Ports
o
The Primary and Secondary Ports
must both be running at the same
frequency
Compliant with the following specifications:
o
PCI Local Bus Specification,
Revision 2.2
o
PCI-to-PCI Bridge Architecture
Specification, Revision 1.1
o
Advanced Configuration Power
Interface
(ACPI)
Specification
o
PCI Power Management
Specification, Revision 1.1
Concurrent primary and secondary port
operation
Provides internal arbitration for one set of 4
secondary bus masters
o
Programmable 2-level priority
arbiter
o
Disable control to allow use of an
external arbiter
Supports posted write buffers in both
directions (downstream and upstream)
Two 128-byte FIFO’s for delay transactions
Two 128-byte FIFO’s for posted memory
transactions
Enhanced address decoding
o
32-bit I/O address range
o
32-bit memory-mapped I/O address
range
o
64-bit prefetchable address range
o
VGA addressing and VGA palette
snooping
o
ISA-aware mode for legacy support
in the first 64KB of I/O address
range
3.3V core; 3.3V and 5V PCI I/O interface
160-pin MQFP package
Intel 21152 compatible
PRODUCT DESCRIPTION
The PI7C8152 is a 2-port PCI-to-PCI Bridge
designed to be fully compliant with the
PCI
Local Bus Specification, Revision 2.2.
Both the
primary and secondary ports are specified to run
at 32-bit / 66 MHz or 33 MHz (both ports must
be running at the same frequency).
The PI7C8152 supports synchronous bus
transactions between devices on the primary bus
and the secondary bus. The two buses can
operate in concurrent mode, resulting in added
increase in system performance. Concurrent bus
operation off-loads and isolates traffic on a
single bus by allowing a master and target on the
same bus to communicate with each other while
the other bus is busy.
The
PCI Local Bus Specification
denotes loading
restrictions on the PCI bus. The PI7C8152
allows designers to expand the loading capability
by adding a second PCI bus. On motherboards,
more PCI slots or devices can then be added on
this second PCI bus. On add-in cards, more than
one device can now reside on the add-in card
(PCI
Local Bus Specifications
specify that each
add-in card may only have one device because
there may only be one connection per PCI signal
in the add-in card connector).
·
·
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·
·
·
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ORDERING INFORMATION
PART NUMBER
PI7C8152MA
SPEED
66 MHz
or
33 MHz
PACKAGE
160-MQFP
·
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Page 1
PERICOM SEMICONDUCTOR CORPORATION
2380 Bering Drive
·
San Jose, CA 95131
·
(800) 435-0800
·
Fax (408) 435-1100
·
http://www.pericom.com
11/04/2002, REVISION 1.0
PI7C8152
2-PORT PCI-to-PCI BRIDGE
DATA BRIEF
PI7C8152 BLOCK DIAGRAM
PRIMARY
CLOCK
SECONDARY
CLOCK
CONFIGURATION
REGISTER
ARBITER
REQ/GNT
TRANSACTION
QUEUE & DATA
BUFFERS
TRANSACTION
QUEUE & DATA
BUFFERS
PRIMARY
MASTER/TARGET
INTERACE/CONTROL
MASTER/TARGET
INTERACE/CONTROL
PI7C8152 APPLICATION EXAMPLE
Allows more
than one device
to plug into a
single PCI slot
CPU
GRAPHICS
A
B
C
P2P
DISK
STORAGE
CORE
LOGIC
OTHER
I/O
Primary PCI Bus
PCI-to-PCI
Bridge
Secondary PCI Bus
Extends the
number of PCI
slots or loads
on a system
Page 2
PERICOM SEMICONDUCTOR CORPORATION
2380 Bering Drive
·
San Jose, CA 95131
·
(800) 435-0800
·
Fax (408) 435-1100
·
http://www.pericom.com
11/04/2002, REVISION 1.0
SECONDARY INTERACE
PRIMARY INTERFACE
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