TS86101G2B
4:1 10-bit 1.2 Gsps MUXDAC
Datasheet
Main Features
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•
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•
•
•
•
•
•
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10-bit Resolution
1.2 Gsps Guaranteed Conversion Rate, 1.4 Gsps Typical
4:1 Integrated Parallel MUX
PECL/LVDS Differential Data and Clock Inputs
2 Vpp Differential Analog Output Swing
Output Impedance: 50Ω Single-ended, 100Ω Differential
Programmable DSP Clock
Power Up Reset for Easy Synchronization of Several DACs
Dual Power Supply: ±5V
CBGA 255 Package for =
C
and
V
Grades
CI-CGA 255 Package for
M
Grade
Evaluation Board TSEV86101G2BG
L
Performance
•
Broadband
– NPR: 49 dB at Fs = 1.2 Gsps: 9.5 bits equivalent (20 MHz to 580 MHz Broadband Pattern, 25 MHz Notch Centered Around
250 MHz)
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Single Tone
– SFDR Baseband (Full First Nyquist Zone):
70 dBFS at Fs = 1.0 Gsps
68 dBFS at Fs = 1.2 Gsps
– SFDR in Third Nyquist Zone
69 dBFS at Fs = 1.2 Gsps, Fout = 5 × Fs/4
> 60 dBFS at Fs = 1.2 Gsps, Fout = 5 × Fs/4 ±150 MHz (–12 dBm Constant Output Power over 300 MHz Instantaneous
Bandwidth)
•
Multi-tone
– Eight-tone IMD: 70 dBFS at Fs = 1.2 Gsps and 500 MHz Baseband
Eight Tones Ranging from 80 MHz to 517.5 MHz, 62.5 MHz Spacing
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Total Power Dissipation = 3.6W
Applications
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Direct Digital Synthesis (DDS) for Broadband Applications
Digital Beam Forming
Automatic Test Equipment (ATE)
Instrumentation: Arbitrary Waveform Generator
Screening
•
Temperature Range:
– C grade: 0°C < T
C
; T
J
< 90°C
– V grade: –40°C < T
C
; T
J
< 110°C
– M grade: –55°C < T
C
; T
J
< 125°C
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e2v semiconductors SAS 2009
0992D–BDC–04/09
TS86101G2B
1. Description
The TS86101G2B is a 10-bit 1.2 Gsps DAC with an integrated 4:1 multiplexer, allowing easy interfacing with standard
FPGAs. The enhanced linearity and Noise Power Ratio (NPR) performance (9.5 bits equivalent at 1.2 Gsps) over 550 MHz
instantaneous bandwidth make this product particularly suitable for high-end applications such as arbitrary waveform gen-
erators and broadband DDS systems.
2. Specifications
Table 2-1.
Parameter
Positive digital power supply
Negative digital power supply
Negative analog power supply
Maximum difference between negative supply voltages
Digital inputs
Port
Y
= A/B/C/D
Maximum difference digital inputs
Port
Y
= A/B/C/D
Data ready clock input
Maximum difference between D_CK_T and D_CK_F
Master clock input
Maximum difference between CW_IN_T and CW_IN_F
Digital shift select voltage
Maximum junction temperature
Storage temperature
Absolute Maximum Ratings
Symbol
V
CCD
V
EED
V
EEA
V
EED
- V
EEA
<Y0_T; Y9_T> or
<Y0_F; Y9_F>
<Y0_T; Y9_T>
<Y0_F; Y9_F>
D_CK_T, D_CK_F
D_CK_T, D_CK_F
CW_IN_T, CW_IN_F
CW_IN_T, CW_IN_F
CS
T
J
Tstg
T
balls
Comments
Value
GND to 6.0
–6.0 to GND
–6.0 to GND
0.7
V
IL
> –0.25
V
IH
< 5.5
V
IH
- V
IL
< 1.4
V
IL
> –0.25
V
IH
< 5.5
V
IH
- V
IL
< 1.4
V
IL
> –3.5
V
IH
< 0.75
V
IH
- V
IL
< 1.2
GND to V
CCD
135
–65 to 150
250 (during 10s max.)
Unit
V
V
V
V
V
Vp
V
Vp
V
Vp
V
°C
°C
°C
Lead temperature
Notes:
1. Maximum ratings are limiting values only (referenced to GND = 0V), and are to be applied individually, while other parame-
ters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. The use of a
thermal heat sink is mandatory (refer to
“Thermal and Moisture Characteristics” on page 36.)
2. Maximum ratings enable active inputs with MUXDAC power off.
3. Maximum ratings enable floating inputs with MUXDAC power on.
2
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
Table 2-2.
Parameter
Recommended Conditions of Use
Symbol
V
CCD
V
EED
V
EEA
Comments
Typ
5
–5
–5
Unit
V
V
V
Positive digital power supply
Negative digital power supply
(1)
Negative analog power supply
(1)
Differential digital inputs
Port
Y
= A, B, C, D
V
IH
V
IL
Swing (on each single-ended input)
Differential data ready clock inputs
V
IH
V
IL
Swing (on each single-ended input)
Differential master clock inputs
Swing (on CW_IN_T)
Master clock input power level
<Y0_T; Y9_T>
<Y0_F; Y9_F>
1.4
1.0
0.2
V
V
Vp
D_CK_T
D_CK_F
1.4
1.0
0.2
Single-ended mode: master clock applied on
CW_IN_T through 10 nF AC capacitor.
CW_IN_F grounded through 10 nF AC capacitor
Single-ended mode
Commercial “C” grade
Industrial “V” grade
Military “M” grade
V
V
Vp
CW_IN_T
CW_IN_F
PCW_IN_T
PCW_IN_F
0.316
Vp
0
0°C < T
C
;
T
J
< 90°C
–40°C < T
C
;
T
J
< 110°C
–55°C < T
C
;
T
J
< 125°C
dBm
Operating temperature range
T
C
, T
J
°C
Note:
1. V
EAA
and V
EED
are internally short circuited through the chip substrate (4Ω equivalent resistance between V
EEA
and V
EED
).
Therefore, V
EEA
and V
EED
must be externally driven by the same power supply source with V
EEA
and V
EED
board planes
short circuited, and power supply connected to the V
EEA
plane.
3
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
2.1
Electrical Operating Characteristics
Electrical Operating Characteristics: V
CCD
= 5V, V
EEA
and V
EED
= –5V, LVDS Input Level, T
J
= 85°C
Test
Level
4
4
1600
Table 2-3.
Parameter
Resolution
ESD protection
Power Requirements
Positive supply voltage (digital)
Positive supply current
Negative supply voltage
Analog
Digital
Negative supply current
Analog
Digital
Power dissipation
Digital Inputs and Data Ready Clock Input
Logic compatibility
Digital input voltages (differential):
- Logic
0
voltage
- Logic
1
voltage
- Swing (on each single-ended input)
- Common mode
Input capacitance (die) from each single-ended input to ground
Input resistance:
- Single-ended
- Differential
Master Clock Input (CW_IN_T, CW_IN_F)
Logic compatibility
AC coupled digital input voltages (differential):
Single-ended operation:
- Swing (on single-ended input used)
Differential operation:
- Swing (on each singled-ended input)
Power level:
- Single-ended operation
- Differential operation (power on each single-ended input)
Input capacitance (die)
Input resistance:
- Single-ended
- Differential
Symbol
Min
Typ
10
Max
Unit
bits
V
V
CCD
I
VCCD
V
EEA
V
EED
I
VEEA
I
VEED
P
D
1
1
4.75
5
33
5.25
40
V
mA
1
–5.25
–5.25
–5
–5
–4.75
–4.75
V
V
1
380
300
430
340
4.0
mA
mA
W
1
3.6
2.5V PECL/3.3V PECL/LVDS
V
IL
V
IH
Vp
CM
4
4
–0.2
0.3
0.1
0.2
1.0
1.4
0.2
1.2
2
2.7
2.9
0.7
2.8
V
V
Vp
V
pF
Ω
Ω
1
50
100
ECL/PECL/LVDS (providing AC coupling
capacitors)
Vp
Vp
4
0.2
0.1
–4
–10
0.3
0.15
0.8
0.4
8
2
Vp
Vp
dBm
dBm
pF
Ω
Ω
4
4
2
50
100
4
4
0992D–BDC–04/09
e2v semiconductors SAS 2009
TS86101G2B
Table 2-3.
Electrical Operating Characteristics: V
CCD
= 5V, V
EEA
and V
EED
= –5V, LVDS Input Level, T
J
= 85°C
(Continued)
Symbol
Test
Level
Min
Typ
Max
Unit
Parameter
DSP Clock Output (DSP_CK_T, DSP_CK_F)
Logic compatibility
Digital output voltages (true or false signals):
- Logic
0
voltage
- Logic
1
voltage (only depends on V
CCD
)
- Swing (on each single-ended output)
- Common mode voltage
Analog Outputs
Differential full-scale output voltage (100Ω differentially terminated)
Full-scale output power (differential output)
Full-scale power at 1/
2
balun output 50Ω terminated)
4
PECL/LVDS (providing AC coupling capacitors and pull-
down resistors to change the common mode voltage)
V
CCD
–0.38
V
CCD
–0.35
V
CCD
–0.16
0.19
4.75
V
CCD
–0.30
V
CCD
–0.13
0.22
V
V
Vpp
V
V
OL
V
OH
Vpp
CM
1
V
CCD
–0.22
0.15
(OUT_T,
OUT_F)
P
OUT
D
P
OUT
B
OUT_T
or
OUT_F
P
OUT
S
4
2
7
7
Vpp
dBm
dBm
Single-ended full-scale output voltage (50Ω terminated)
Full-scale output power (single-ended output)
4
1
4
Vpp
dBm
Single ended mid-scale output voltage (50Ω terminated)
Output capacitance (from each single-ended output to ground)
Output VSWR (50Ω // 2 pF load on each single-ended output):
- From DC to 600 MHz
- From 600 MHz to 1.5 GHz
Deviation from theoretical Sinx/x
(50Ω // 2 pF load on each single ended output at Fs = 1.2 Gsps)
Fout up to 600 MHz
AC Performance
VSWR
C
OUT
5
4
–600
1
1.25:1
2.75:1
mV
pF
4
4
–1.5
–2.0
dB
Single tone
Spurious free dynamic range
(1)
:
Fs = 600 Msps; Fout = 12.5 MHz (–6 dBFS)
4
61
67
57
Fs = 600 Msps; Fout = 287.5 MHz (–6 dBFS)
SFDR
1
67
58
Fs = 1.2 Gsps; Fout = 25 MHz (–6 dBFS)
4
64
53
Fs = 1.2 Gsps; Fout = 575 MHz (–6 dBFS)
4
63
65
71
62
72
62
68
58
68
dBc
dBFS
dBc
dBFS
dBc
dBFS
dBc
dBFS
5
0992D–BDC–04/09
e2v semiconductors SAS 2009
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