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Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> SP5655SKG/MPAD
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SP5655SKG/MPAD

Description
PLL Frequency Synthesizer, BIPolar, PDSO16, MINIATURE, PLASTIC, DIP-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size432KB，12 Pages
ManufacturerZarlink Semiconductor (Microsemi)
Websitehttp://www.zarlink.com/
Download Datasheet Parametric Compare View All

SP5655SKG/MPAD Overview

PLL Frequency Synthesizer, BIPolar, PDSO16, MINIATURE, PLASTIC, DIP-16

SP5655SKG/MPAD Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerZarlink Semiconductor (Microsemi)
package instructionSOP, SOP16,.25
Reach Compliance Codeunknown
Analog Integrated Circuits - Other TypesPLL FREQUENCY SYNTHESIZER
JESD-30 codeR-PDSO-G16
JESD-609 codee0
length9.9 mm
Number of functions1
Number of terminals16
Maximum operating temperature80 °C
Minimum operating temperature-20 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply5 V
Certification statusNot Qualified
Maximum seat height1.91 mm
Maximum supply current (Isup)40 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyBIPOLAR
Temperature levelCOMMERCIAL EXTENDED
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width3.9 mm

SP5655SKG/MPAD Preview

SP5655
2·7GHz Bidirectional I
2
C Bus Controlled Synthesiser
Advance Information
DS3743
ISSUE 5.0
June 1998
The SP5655 is a single chip frequency synthesiser
designed for TV tuning systems. Control data is entered in
the standard I
2
C BUS format. The device contains 2
addressable current limited outputs and 4 addressable
bidirectional open-collector ports, one of which is a 3-bit
ADC. The information on these ports can be read via the I
2
C
BUS. the device has one fixed I
2
C BUS address and 3
programmable addresses, programmed by applying a specific
input voltage to one of the current limited outputs. This
enables two or more synthesisers to be used in a system.
Ordering Information
SP5655 KG/MPAS
(Tubes)
SP5655S KG/MPAD
(Tape and reel)
FEATURES
I
Complete 2·7GHz Single Chip System
I
High Sensitivity RF Inputs
CHARGE PUMP
CRYSTAL Q1
CRYSTAL Q2
SDA
SCL
1
2
3
4
5
6
7
8
16
15
14
13
DRIVE OUTPUT
V
EE
RF INPUT
RF INPUT
V
CC
P0 OUTPUT PORT
P3 OUTPUT PORT/
ADD SELECT
I/O PORT P4
†
I
I
I
I
I
I
I
I
I
I
I
Programmable via I
2
C BUS
Low Power Consumption (5V, 30mA)
Low Radiation
Phase Lock Detector
Varactor Drive Amp Disable
6 Controllable Outputs, 4 Bidirectional
5-Level ADC
Variable I
2
C BUS Address for Multi-tuner Applications
ESD Protection: 4kV, Mil-Std-883C, Method 3015
(1)
Switchable
4512/1024
Reference Divider
Pin and Function Compatible with SP5055S
(2)
(1) Normal ESD handling precautions should be observed.
(2) The SP5055S does not have a switchable reference
division ratio.
SP5655
12
11
10
9
†
I/O PORT P7
*
I/O PORT P6
†
I/O PORT P5
MP16
† = Logic level I/O port
*
= 3-bit ADC input
Fig. 1 Pin connections – top view
APPLICATIONS
I
Satellite TV
I
High IF Cable Tuning Systems
THERMAL DATA
u
JC
= 41°C/W
u
JA
= 111°C/W
SP5655
Advance Information
ELECTRICAL CHARACTERISTICS
T
AMB
=
220°C
to
180°C,
V
CC
=
14·5V
to
15·5V,
reference frequency = 4MHz.
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated.
Value
Characteristic
Pin
Min.
Supply current
Prescaler input voltage
Prescaler input impedance
Prescaler input capacitance
SDA, SCL
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
SDA
Output voltage
Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
External reference input frequency
External reference input amplitude
Output Ports
P0, P3 sink current
P0, P3 leakage current
P4-P7 sink current
P4-P7 leakage current
Input Ports
P3 input current high
P3 input current low
P4, P5, P7 input voltage low
P4, P5, P7 input voltage high
P6 input current high
P6 input current low
12
13,14
13,14
13, 14
4,5
4,5
4,5
4,5
4,5
4
1
1
1
16
6
50
6
170
6
5
500
6400
10
2
2
2
2
11, 10
11, 10
9-6
9-6
10
10
9,8,6
9,8,6
7
7
750
2
70
0·7
10
10
1
10
2
10
0·8
2·7
1
10
2
10
80
1000
8
200
1
1·5
10
200
Parallel resonant crystal (note 2)
Ω
mV p-p
Ω
MHz AC coupled sinewave
mVrms AC coupled sinewave
mA
µA
mA
µA
µA
µA
V
V
µA
µA
V
OUT
= 12V
V
OUT
= 13·2V
V
OUT
= 0·7V
V
OUT
= 13·2V
V pin 10 = V
CC
V pin 10 = 0V
3
0
Typ.
30
50
50
2
5·5
1·5
10
2
10
10
0·4
Max.
40
300
V
CC
= 4·5V to 5·5V (note 1)
mA
mVrms 120MHz to 2·7GHz sinewave,
see Fig. 5
Ω
pF
V
V
µA
µA
µA
V
µA
µA
nA
µA
Units
Conditions
Input voltage = V
CC
Input voltage = 0V
When V
CC
= 0V
Sink current = 3mA
Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 16 = 0·7V
See Table 3 for ADC levels
NOTES
1. Maximum power consumption is 220mW with V
CC
= 5·5V and all ports off.
2. Resistance specified is maximum under all conditions.
2
Advance Information
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to V
EE
and pin 3 at 0V
Parameter
Pin
Min.
Supply voltage
RF input voltage
Port voltage
12
13,14
6-11
6-9
10, 11
Total port output current
Address select voltage
RF input DC offset
Charge pump DC offset
Drive output DC offset
Crystal oscillator DC offset
SDA, SCL input voltage
Storage temperature
Junction temperature
6-9
10
13-14
1
16
2
4,5
20·3
20·3
20·3
20·3
20·3
20·3
2
55
20·3
20·3
20·3
20·3
Value
Max.
7
2·5
14
6
14
50
V
CC
10·3
V
CC
10·3
V
CC
10·3
V
CC
10·3
V
CC
10·3
6
1
150
1
150
V
V p-p
V
V
V
mA
V
V
V
V
V
V
°C
°C
Units
SP5655
Conditions
Port in off state
Port in on state
Port in on state
13
PREAMP
PRESCALER
4
16
15-BIT
PROGRAMMABLE
DIVIDER
F
PD
PHASE
COMP
F
COMP
DIVIDER
4
512/1024
OSC
2
3
Q1
CRYSTAL
Q2
CHARGE PUMP
RF IN
14
F
LOCK
DET
1
POWER
ON DET
POR
5
4
15-BIT LATCH
DIVIDE RATIO
DN
CHARGE
PUMP
F
L
UP
CONTROL DATA
LATCHES
AND
CONTROL LOGIC
4
16
DRIVE/
VARICAP OUT
SCL
SDA
I
2
C BUS
TRANSCEIVER
CP
TO
OS
ADDRESS
SELECT
3-BIT
ADC
LEVEL
3 TTL
COMP
6-BIT LATCH
PORT INFO
2
4
PORT OUTPUT DRIVERS
15
V
CC
V
EE
11
10
9
8
7
6
P0
P3
P4
P5
P6
P7
Fig. 2 Block diagram
3
SP5655
Advance Information
from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0); a
logic 1 to 512, a logic 0 for 1024. The SP5655 differs from the
SP5055 in this respect, only 512 being available on the
SP5055. Note that the comparison frequency is 7·8125kHz
when a 4MHz reference is used, and divide by 512 is selected.
Bit 2 of byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for
±170µA
and a
logic 0 for
±50µA,
allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. When the device is frequency
locked, the charge pump current is internally set to
±50µA
regardless of CP.
Bit 4 of byte 4 (T0) disables the charge pump when it is set
to a logic 1.
Bit 8 of byte 4 (OS) switches the charge pump drive
amplifier’s output off when it is set to a logic 1.
Bit 3 of byte 4 (T1) enables various test modes when set
high. These modes are selected by bits 5, 6 and 7 of byte 4
(TS2, and TS1, TS0) as detailed in Table 5. When T1 is set
low, TS2 and TS1 are assigned a ‘don’t care’ condition, and
TS0 selects the reference divider ratio as previously de-
scribed.
Byte 5 programs the output ports P0 and P3 to P7; a logic
0 for a high impedance output and a logic 1 for low impedance
(on).
FUNCTIONAL DESCRIPTION
The SP5655 is programmed from an I
2
C Bus. Data and
Clock are fed in on the SDA and SCL lines respectively, as
defined by the I
2
C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
LSB of the address byte (R/W) sets the device into write mode
if it is low and read mode if it is high. The Tables in Fig. 3
illustrate the format of the data. The device can be pro-
grammed to respond to several addresses, which enables the
use of more than one synthesiser in an I
2
C Bus system.
Table 4 shows how the address is selected by applying a
voltage to P3.
When the device receives a correct address byte, it pulls
the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are
programmed. When the device is programmed into the read
mode, the controller accepting the data must pull the SDA line
low during all status byte acknowledge periods to read an-
other status byte. If the controller fails to pull the SDA line low
during this period, the device generates an internal STOP
condition, which inhibits further reading.
WRITE Mode (Frequency Synthesis)
When the device is in write mode bytes 2 and 3 select the
synthesised frequency, while bytes 4 and 5 control the output
port states, charge pump, reference divider ratio and various
test modes.
Once the correct address is received and acknowledged,
the first bit of the next byte determines whether that byte is
interpreted as byte 2 or 4; a logic 0 for frequency information
and a logic 1 for control and output port information. When
byte 2 is received the device always expects byte 3 next.
Similarly, when byte 4 is received the device expects byte 5
next. Additional data bytes can be entered without the need
to readdress the device until an I
2
C stop condition is recog-
nised. This allows a smooth frequency sweep for fine tuning
or AFC purposes.
If the transmission of data is stopped mid-byte (for exam-
ple, by another device on the bus) then the previously pro-
grammed byte is maintained.
Frequency data from bytes 2 and 3 are stored in a 15-bit register
and used to control the division ratio of the 15-bit programmable
divider. This is preceded by a divide-by-16 prescaler and amplifier to
give excellent sensitivity at the local oscillator input, see Fig. 5. The
input impedance is shown in Fig. 7.
The programmed frequency can be calculated by multiply-
ing the programmed division ratio by 16 times the comparison
frequency F
COMP
. When frequency data is entered, the phase
comparator, via a charge pump and varicap drive amplifier,
adjusts the local oscillator control voltage until the output of
the programmable divider is frequency and phased locked to
the comparison frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2, or provided by an on-
chip crystal controlled oscillator. The comparison frequency
F
COMP
is derived from the reference frequency via the refer-
ence divider. The reference divider division ratio is switchable
READ Mode
When the device is in read mode the status byte read from
the device on the SDA line takes the form shown in Table 2.
Bit 1 (POR) is the power-on reset indicator and is set to a
logic 1 if the V
CC
supply to the device has dropped below 3V
(at 25˚C), for example, when the device is initially turned on.
The POR is reset to 0 when the read sequence is terminated
by a stop command. When POR is set high (at low V
CC
), the
programmed information is lost and the output ports are all set
to high impedance.
Bit 2 (FL) indicates whether the device is phase locked, a
logic 1 is present if the device is locked, and a logic 0 if the
device is unlocked.
Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
P7, P5 and P4 respectively. A logic 0 indicates a low level and
a logic 1 a high level. If the ports are to be used as inputs they
should be programmed to a high impedance state (logic 1).
These inputs will then respond to data complying with TTL
type voltage levels.
Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
the 5-level ADC. The ADC can be used to feed AFC informa-
tion to the microprocessor from the IF section of the receiver,
as illustrated in the typical application circuit.
APPLICATION
A typical application is shown in Fig. 4. All input/output
interface circuits are shown in Fig. 6. The SP5655 is function and
pin equivalent to the SP5055 device apart from the switchable
reference divider, and has much lower power dissipation, im-
proved RF sensitivity and better ESD performance.
4
Advance Information
SP5655
MSB
Address
Programmable divider
Programmable divider
1
0
2
7
1
2
14
2
6
CP
P6
0
2
13
2
5
T1
P5
0
2
12
2
4
T0
P4
0
2
11
2
3
MA1 MA0
2
10
2
2
2
9
2
1
LSB
0
2
8
2
0
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Charge pump and test bits
1
I/O port control bits
P7
TS2 TS1 TS0 OS
P3
X
X
P0
Table 1 Write data format (MSB transmitted first)
Address
Status byte
1
1
0
I2
0
I1
0
I0
MA1 MA0
A2
A1
1
A0
A
A
Byte 1
Byte 2
POR FL
Table 2 Read data format
A2
1
0
0
0
0
A1
0
1
1
0
0
A0
0
1
0
1
0
Voltage input to P6
0·6V
CC
to 13·2V
0·45V
CC
to 0·6V
CC
0·3V
CC
to 0·45V
CC
0·15V
CC
to 0·3V
CC
0V to 0·15V
CC
MA1 MA0 Address select input voltage
0
0
1
1
0
1
0
1
0V to 0·2V
CC
Always valid
0·3V
CC
to 0·7V
CC
0·8V
CC
to 13·2V
Table 3 ADC levels
T1
0
0
1
1
1
1
1
TS2 TS1 TS0
X
X
0
0
1
1
1
X
X
0
1
0
0
1
0
1
X
X
0
1
X
Table 4 Address selection
Operation mode description
Normal operation, test modes disabled, reference divider ratio = 1024
Normal operation, test modes disabled, reference divider ratio = 512
Charge pump source (down). Status bit FL set to 0
Charge pump sink (up). Status bit FL set to 1
Ports P4, P5, P6, P7set to state X
Port P7 = F
PD
/2; P4, P5, P6 set to state X
Port P7 = F
PD
; P6 = F
COMP
; P4, P5 set to state X
NOTES
X = don’t care
For further details of test modes, see Table 6
Table 5 Operation modes
A
MA1, MA0
CP
T1
T0
TS2, TS1, TS0
OS
P7, P6, P5, P4, P3, P0
POR
FL
I2, I1, I0
A2, A1, A0
X
:
:
:
:
:
:
:
:
:
:
:
:
:
Acknowledge bit
Variable address bits (see Table 4)
Charge Pump current select
Test mode selection
Charge pump disable
Operation mode control bits (see Table 5)
Varactor drive Output disable Switch
Control output port states
Power On Reset indicator
Phase lock detect flag
Digital information from ports P7, P5 and P4 respectively
5-level ADC data from P6 (see Table 3)
Don’t care
Fig. 3 Data formats
5
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

SP5655SKG/MPAD Related Products

SP5655SKG/MPAD SP5655KG/MPAS
Description PLL Frequency Synthesizer, BIPolar, PDSO16, MINIATURE, PLASTIC, DIP-16 PLL Frequency Synthesizer, BIPolar, PDSO16, MINIATURE, PLASTIC, DIP-16
Is it Rohs certified? incompatible incompatible
Maker Zarlink Semiconductor (Microsemi) Zarlink Semiconductor (Microsemi)
package instruction SOP, SOP16,.25 SOP, SOP16,.25
Reach Compliance Code unknown unknown
Analog Integrated Circuits - Other Types PLL FREQUENCY SYNTHESIZER PLL FREQUENCY SYNTHESIZER
JESD-30 code R-PDSO-G16 R-PDSO-G16
JESD-609 code e0 e0
length 9.9 mm 9.9 mm
Number of functions 1 1
Number of terminals 16 16
Maximum operating temperature 80 °C 80 °C
Minimum operating temperature -20 °C -20 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP SOP
Encapsulate equivalent code SOP16,.25 SOP16,.25
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
power supply 5 V 5 V
Certification status Not Qualified Not Qualified
Maximum seat height 1.91 mm 1.91 mm
Maximum supply current (Isup) 40 mA 40 mA
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount YES YES
technology BIPOLAR BIPOLAR
Temperature level COMMERCIAL EXTENDED COMMERCIAL EXTENDED
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING
Terminal pitch 1.27 mm 1.27 mm
Terminal location DUAL DUAL
width 3.9 mm 3.9 mm

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