IC 8-BIT, MICROCONTROLLER, PDIP64, 0.750 INCH, SHRINK, PLASTIC, DIP-64, Microcontroller
TMP90PH44N Parametric
Parameter Name
Attribute value
Is it Rohs certified?
incompatible
Maker
Toshiba Semiconductor
Parts packaging code
DIP
package instruction
SDIP,
Contacts
64
Reach Compliance Code
unknown
Has ADC
YES
Address bus width
16
bit size
8
boundary scan
NO
maximum clock frequency
16 MHz
DAC channel
NO
DMA channel
NO
External data bus width
8
Format
FIXED POINT
Integrated cache
NO
JESD-30 code
R-PDIP-T64
JESD-609 code
e0
length
57.5 mm
low power mode
YES
Number of DMA channels
Number of external interrupt devices
3
Number of I/O lines
54
Number of serial I/Os
1
Number of terminals
64
Number of timers
3
On-chip data RAM width
8
On-chip program ROM width
8
Maximum operating temperature
70 °C
Minimum operating temperature
-20 °C
PWM channel
NO
Package body material
PLASTIC/EPOXY
encapsulated code
SDIP
Package shape
RECTANGULAR
Package form
IN-LINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)
240
Certification status
Not Qualified
RAM (number of words)
512
rom(word)
16384
ROM programmability
OTPROM
Maximum seat height
5 mm
Maximum slew rate
50 mA
Maximum supply voltage
5.5 V
Minimum supply voltage
4.5 V
Nominal supply voltage
5 V
surface mount
NO
technology
CMOS
Temperature level
COMMERCIAL
Terminal surface
Tin/Lead (Sn/Pb)
Terminal form
THROUGH-HOLE
Terminal pitch
1.778 mm
Terminal location
DUAL
Maximum time at peak reflow temperature
NOT SPECIFIED
width
19.05 mm
uPs/uCs/peripheral integrated circuit type
MICROCONTROLLER
TMP90PH44N Preview
TOSHIBA
TLCS-90 Series
CMOS 8–Bit Microcontrollers
TMP90PH44N/TMP90PH44F
1. Outline and Characteristics
The TMP90PH44 is a system evaluation LSI having a built-in
One-Time PROM for (16K byte) for TMP90C844.
A programming and verification for the internal PROM is
achieved by using a general EPROM programmer with an
adapter socket.
TMP90PH44
The function of this device is exactly the same as the
TMP90C844 by programming to the internal PROM.
The different points between TMP90PH44 and
TMP90C844 are the memory size (ROM/RAM).
The TMP90PH44N is in a Shrink Dual Inline Package.
(SDIP64-P-750)
The TMP90PH44F is in a Quad Flat Package.
(QFP64-P-1420A)
The following are the memory map of TMP90PH44 and
TMP90C844.
Figure 1.1. TMP90PH44
Figure 1.2. TMP90C844
Parts No.
TMP90PH44N
TMP90PH44F
ROM
RAM
Package
64-SDIP
Adapter Socket
No.
BM1148
(Under Development)
BM1149
(Under Development)
OTP
16384 x 8bit
512 x 8bit
64-QFP
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
1/20
TMP90PH44
Figure 1. 3. TMP90PH44 Block Diagram
2/20
TOSHIBA CORPORATION
TMP90PH44
2. Pin Assignment and Functions
The TMP90PH44 pin assignment input/output pins name and
functions are shown below.
2.1 Pin Assignment Diagram
The TMP90PH44N pin assignment are shown in Figure 2.1 (1).
Figure 2.1 (1). Pin Assignment (Shrink DIP)
TOSHIBA CORPORATION
3/20
TMP90PH44
The TMP90PH44F pin assignment are shown in Figure 2.1 (2).
Figure 2.1 (2). Pin Assignment (Flat Package)
4/20
TOSHIBA CORPORATION
TMP90PH44
2.2 Pin Names and Functions
The TMP90PH44 has MCU mode and PROM mode.
(1)
MCU Mode (The TMP90C844 and the TMP90PH44
are pin compatible).
Table 2.2 Pin Names and Functions (1/2)
Pin Name
P00 ~ P07
/AD0 ~ AD7
P10 ~ P17
/A8 ~ A15
P20 ~ P27
/SB0 ~ SB7
/WAIT
P30 ~ P37
/SWR
/SRD
/SCS
C/D
/STA
RxD
/SCLK
/TxD
P40 ~ P47
/TO1, 3, 4, 5
/TI0, 2, 4, 5
/INT0
/INT1
INT2
P50 ~ P53
/AN0 ~ AN3
P56
/RD
No. of pins
8
I/O or tristate
I/O
/Tristate
I/O
Output
I/O
Function
Port 0: An 8-bit I/O port. Each bit can be set for input or output.
Address/Data bus: Operates as an 8-bit bidirectional address bus or data bus when using external memory
Port 1: An 8-bit I/O port. Each bit can be set for input or output.
Address bus:Operates as an address bus (upper 8 bits) when using external memory.
Port 2: An 8-bit I/O port. Each bit can be set for input or output.
Slave bus: When used a s a slave processor,
operates as the slave bue for the transfer data to and from the master processor.
Wait: Used as an input pin when memory or perpheral LSIs with slow access times are controlled.
Port 3: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor).
Slave write: The strobe signal input to write data from the master processor.
Slave read: The strobe signal used by the master processor to read data.
Slave chip select: The chip select signal input from the master processor.
Command/data: The command/data select signal input from the master processor.
Status output: Used to report the slave bus status to the master processor.
Serial receive data
Serial clock
Serial transmit data
Port 4: 8-bit I/O port which allows I/O section on bit basis (with programmable pull-up resistor).
Timer outputs 1, 3, 4, and 5: Output for timer 0, or timer 1, timer 2, timer 3 and timer 4 (2 lines).
Timer inputs 0, 2, 4, and 5: Input for timer 0, or timer 1, timer 2 and timer 4 (2 lines).
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