128K
X24128
400KHz 2-Wire Serial E
2
PROM with Block Lock
TM
DESCRIPTION
16K x 8 Bit
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Save Critical Data with Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E
2
PROM Array)
—Software Write Protection
—Programmable Hardware Write Protect
In Circuit Programmable ROM Mode
400KHz 2-Wire Serial Interface
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1
µ
A
1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Versions
32 Word Page Write Mode
—Minimizes Total Write Time Per Word
Internally Organized 16K x 8
Bidirectional Data Transfer Protocol
Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
14-Lead SOIC
16-Lead SOIC
8-Lead PDIP
The X24128 is a CMOS Serial E
2
PROM, internally
organized 16K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
Three device select inputs (S
0
–S
2
) allow up to eight
devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, FFFFh, provides three write protection features:
Software Write Protect, Block Lock Protect, and
Programmable Hardware Write Protect. The Software
Write Protect feature prevents any nonvolatile writes to
the device until the WEL bit in the Write Protect
Register is set. The Block Lock Protection feature
gives the user four array block protect options, set by
programming two bits in the Write Protect Register.
The Programmable Hardware Write Protect feature
allows the user to install the device with WP tied to
V
CC
, write to and Block Lock the desired portions of
the memory array in circuit, and then enable the In
Circuit Programmable ROM Mode by programming the
WPEN bit HIGH in the Write Protect Register. After
this, the Block Locked portions of the array, including
the Write Protect Register itself, are permanently
protected from being erased.
FUNCTIONAL DIAGRAM
SERIAL E
2
PROM DATA
AND ADDRESS (SDA)
DATA REGISTER
Y DECODE LOGIC
COMMAND
DECODE
AND
CONTROL
LOGIC
BLOCK LOCK AND
WRITE PROTECT
CONTROL LOGIC
S2
S1
S0
DEVICE
SELECT
LOGIC
WRITE
PROTECT
REGISTER
8K x 8
SERIAL E
2
PROM
ARRAY
16K x 8
4K x 8
SCL
PAGE
DECODE
LOGIC
4K x 8
WP
©
Xicor, 1995, 1996 Patents Pending
7027-1.3 5/14/97 T2/C0/D2 SH
WRITE VOLTAGE
CONTROL
7027 FM 01
1
Characteristics subject to change without notice
X24128
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the
Pull-up resistor selection graph at the end of this data
sheet.
Device Select (S
0
, S
1
, S
2
)
The device select inputs (S
0
, S
1
, S
2
) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V
SS
or V
CC
as appro-
priate. If actively driven, they must be driven with
CMOS levels (driven to V
CC
or V
SS
).
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write
Protection is disabled. When this input is held HIGH,
and the WPEN bit in the Write Protect Register is set
HIGH, the Write Protect Register is protected,
preventing changes to the Block Lock Protection and
WPEN bits.
.344”
PIN NAMES
Symbol
S
0
, S
1
, S
2
SDA
SCL
WP
V
SS
V
CC
NC
Description
Device Select Inputs
Serial Data
Serial Clock
Write Protect
Ground
Supply Voltage
No Connect
7027 FM T01
PIN CONFIGURATION
Not to scale
14 Lead SOIC
S0
S1
NC
NC
NC
S2
VSS
1
2
3
4
5
6
7
.244”
X24128
14
13
12
11
10
9
8
VCC
WP
NC
NC
NC
SCL
SDA
16 Lead SOIC
S0
S1
NC
.394”
NC
NC
NC
S2
VSS
1
2
3
4
5
6
7
8
.244”
X24128
16
15
14
13
12
11
10
9
VCC
WP
NC
NC
NC
NC
SCL
SDA
8 Lead PDIP
S0
.430”
S1
S2
VSS
1
2
3
4
.325”
X24128
8
7
6
5
VCC
WP
SCL
SDA
7027 FM 02
2
X24128
DEVICE OPERATION
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and
receive operations. Therefore, the device will be
considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
7027 FM 03
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
7027 FM 04
3
X24128
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
7027 FM 05
4
X24128
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S
0
, S
1
, and S
2
. This allows up to 8
devices to share a single bus. These bits are
compared to the S
0
, S
1
, and S
2
device select input
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a read operation is selected. When it is zero then
a write operation is selected. Refer to figure 4. After
loading the Slave Address Byte from the SDA bus, the
device compares the device type bits with the value
“1010” and the device select bits with the status of the
Figure 4. Device Addressing
device select input pins. If the compare is not successful,
no acknowledge is output during the ninth clock cycle
and the device returns to the standby mode.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in figure 4.
The internal organization of the E
2
array is 512 pages by
32 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 5 of the Word Address Byte 0. The byte
address is contained in bits 4 through 0 of the Word
Address Byte 0. See figure 4.
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1
0
1
0
S2
S1
S0
R/ W
SLAVE ADDRESS BYTE
HIGH ORDER WORD ADDRESS
0
0
A13
A12
A11 A10
A9
A8
X24128 WORD ADDRESS BYTE 1
LOW ORDER WORD ADDRESS
A7
A6
A5
A4
A3
A2
A1
A0
WORD ADDRESS BYTE 0
D7
D6
D5
D4
D3
D2
D1
D0
DA BYTE
TA
7027 FM 06
5
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