MCP3204/3208
2.7V 4-Channel/8-Channel 12-Bit A/D Converters
with SPI
™
Serial Interface
Features
•
•
•
•
•
•
•
•
•
•
•
•
12-bit resolution
± 1 LSB max DNL
± 1 LSB max INL (MCP3204/3208-B)
± 2 LSB max INL (MCP3204/3208-C)
4 (MCP3204) or 8 (MCP3208) input channels
Analog inputs programmable as single-ended or
pseudo-differential pairs
On-chip sample and hold
SPI serial interface (modes 0,0 and 1,1)
Single supply operation: 2.7V - 5.5V
100 ksps max. sampling rate at V
DD
= 5V
50 ksps max. sampling rate at V
DD
= 2.7V
Low power CMOS technology:
- 500 nA typical standby current, 2 µA max.
- 400 µA max. active current at 5V
Industrial temp range: -40°C to +85°C
Available in PDIP, SOIC and TSSOP packages
Description
The Microchip Technology Inc. MCP3204/3208
devices are successive approximation 12-bit Analog-
to-Digital (A/D) Converters with on-board sample and
hold circuitry. The MCP3204 is programmable to pro-
vide two pseudo-differential input pairs or four single-
ended inputs. The MCP3208 is programmable to pro-
vide four pseudo-differential input pairs or eight single-
ended inputs. Differential Nonlinearity (DNL) is speci-
fied at ±1 LSB, while Integral Nonlinearity (INL) is
offered in ±1 LSB (MCP3204/3208-B) and ±2 LSB
(MCP3204/3208-C) versions.
Communication with the devices is accomplished using
a simple serial interface compatible with the SPI proto-
col. The devices are capable of conversion rates of up
to 100 ksps. The MCP3204/3208 devices operate over
a broad voltage range (2.7V - 5.5V). Low current
design permits operation with typical standby and
active currents of only 500 nA and 320 µA, respec-
tively. The MCP3204 is offered in 14-pin PDIP, 150 mil
SOIC and TSSOP packages. The MCP3208 is offered
in 16-pin PDIP and SOIC packages.
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•
Applications
•
•
•
•
Sensor Interface
Process Control
Data Acquisition
Battery Operated Systems
Functional Block Diagram
V
DD
V
REF
CH0
CH1
V
SS
Package Types
PDIP, SOIC, TSSOP
CH0
CH1
CH2
CH3
NC
NC
DGND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
V
REF
AGND
CLK
D
OUT
D
IN
CS/SHDN
Input
Channel
Mux
DAC
Comparator
CH7*
MCP3204
Sample
and
Hold
Control Logic
12-Bit SAR
Shift
Register
PDIP, SOIC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
V
REF
AGND
CLK
D
OUT
D
IN
CS/SHDN
DGND
CS/SHDN D
IN
CLK
D
OUT
* Note:
Channels 5-7 available on MCP3208 Only
©
2007 Microchip Technology Inc.
MCP3208
DS21298D-page 1
MCP3204/3208
1.0
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
V
DD
DGND
AGND
CH0-CH7
CLK
D
IN
D
OUT
CS/SHDN
V
REF
Function
+2.7V to 5.5V Power Supply
Digital Ground
Analog Ground
Analog Inputs
Serial Clock
Serial Data In
Serial Data Out
Chip Select/Shutdown Input
Reference Voltage Input
Absolute Maximum Ratings*
V
DD
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
DD
+0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins.............................................> 4 kV
*Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V,
T
AMB
= -40°C to +85°C,f
SAMPLE
= 100 ksps and f
CLK
= 20*f
SAMPLE
Parameters
Conversion Rate
Conversion Time
Analog Input Sample Time
Throughput Rate
DC Accuracy
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Dynamic Performance
Total Harmonic Distortion
Signal to Noise and Distortion
(SINAD)
Spurious Free Dynamic
Range
Reference Input
Voltage Range
Current Drain
0.25
—
—
—
100
0.001
V
DD
150
3.0
V
µA
µA
Note 2
CS = V
DD
= 5V
—
—
—
-82
72
86
—
—
—
dB
dB
dB
V
IN
= 0.1V to 4.9V@1 kHz
V
IN
= 0.1V to 4.9V@1 kHz
V
IN
= 0.1V to 4.9V@1 kHz
INL
DNL
—
—
—
—
—
12
±0.75
±1.0
±0.5
±1.25
±1.25
±1
±2
±1
±3
±5
bits
LSB
LSB
LSB
LSB
MCP3204/3208-B
MCP3204/3208-C
No missing codes
over-temperature
t
CONV
t
SAMPLE
f
SAMPLE
—
—
—
—
1.5
—
—
100
50
12
clock
cycles
clock
cycles
ksps
ksps
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 2.7V
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to V
REF
levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,
for more information.
DS21298D-page 2
©
2007 Microchip Technology Inc.
MCP3204/3208
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V,
T
AMB
= -40°C to +85°C,f
SAMPLE
= 100 ksps and f
CLK
= 20*f
SAMPLE
Parameters
Analog Inputs
Input Voltage Range for CH0-
CH7 in Single-Ended Mode
Input Voltage Range for IN+ in
pseudo-differential Mode
Input Voltage Range for IN- in
pseudo-differential Mode
Leakage Current
Switch Resistance
Sample Capacitor
Digital Input/Output
Data Coding Format
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current
Pin Capacitance
(All Inputs/Outputs)
Timing Parameters
Clock Frequency
Clock High Time
Clock Low Time
CS Fall To First Rising CLK
Edge
Data Input Setup Time
Data Input Hold Time
CLK Fall To Output Data Valid
CLK Fall To Output Enable
CS Rise To Output Disable
CS Disable Time
D
OUT
Rise Time
D
OUT
Fall Time
Power Requirements
Operating Voltage
Operating Current
Standby Current
V
DD
I
DD
I
DDS
2.7
—
—
—
—
320
225
0.5
5.5
400
—
2.0
V
µA
µA
V
DD
=V
REF
= 5V, D
OUT
unloaded
V
DD
=V
REF
= 2.7V, D
OUT
unloaded
CS = V
DD
= 5.0V
f
CLK
t
HI
t
LO
t
SUCS
t
SU
t
HD
t
DO
t
EN
t
DIS
t
CSH
t
R
t
F
—
—
250
250
100
—
—
—
—
—
500
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.0
1.0
—
—
—
50
50
200
200
100
—
100
100
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Figures 1-2 and 1-3 (Note
1)
See Figures 1-2 and 1-3 (Note
1)
See Figures 1-2 and 1-3
See Figures 1-2 and 1-3
See Figures 1-2 and 1-3
V
DD
= 5V (Note
3)
V
DD
= 2.7V (Note
3)
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
C
IN
,C
OUT
—
4.1
—
-10
-10
—
Straight Binary
0.7 V
DD
—
—
—
—
—
—
—
—
0.3 V
DD
—
0.4
10
10
10
V
V
V
V
µA
µA
pF
I
OH
= -1 mA, V
DD
= 4.5V
I
OL
= 1 mA, V
DD
= 4.5V
V
IN
= V
SS
or V
DD
V
OUT
= V
SS
or V
DD
V
DD
= 5.0V (Note
1)
T
AMB
= 25°C, f = 1 MHz
V
SS
IN-
V
SS
-100
—
—
—
—
—
—
0.001
1000
20
V
REF
V
REF
+IN-
V
SS
+100
±1
—
—
mV
µA
Ω
pF
See Figure 4-1
See Figure 4-1
V
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to V
REF
levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,
for more information.
©
2007 Microchip Technology Inc.
DS21298D-page 3
MCP3204/3208
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics:
Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, V
REF
= 5V,
T
AMB
= -40°C to +85°C,f
SAMPLE
= 100 ksps and f
CLK
= 20*f
SAMPLE
Parameters
Temperature Ranges
Specified Temperature Range
Operating Temperature
Range
Storage Temperature Range
Thermal Package Resistance
Thermal Resistance,
14L-PDIP
Thermal Resistance,
14L-SOIC
Thermal Resistance,
14L-TSSOP
Thermal Resistance,
16L-PDIP
Thermal Resistance,
16L-SOIC
θ
JA
θ
JA
θ
JA
θ
JA
θ
JA
—
—
—
—
—
70
108
100
70
90
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
T
A
T
A
T
A
-40
-40
-65
—
—
—
+85
+85
+150
°C
°C
°C
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graphs that relate linearity performance to V
REF
levels.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity
performance, particularly at elevated temperatures. See Section 6.2, “Maintaining Minimum Clock Speed”,
for more information.
t
CSH
CS
t
SUCS
t
HI
CLK
t
SU
D
IN
t
HD
t
LO
MSB IN
t
EN
t
DO
Null Bit
MSB OUT
t
R
t
F
t
DIS
LSB
D
OUT
FIGURE 1-1:
Serial Interface Timing.
DS21298D-page 4
©
2007 Microchip Technology Inc.
MCP3204/3208
1.4V
Test Point
V
DD
3 kΩ
D
OUT
C
L
= 100 pF
Test Point
D
OUT
100 pF
V
SS
3 kΩ
V
DD
/2
t
DIS
Waveform 2
t
EN
Waveform
t
DIS
Waveform 1
Voltage Waveforms for t
R
, t
F
D
OUT
t
R
t
F
CLK
Voltage Waveforms for t
DO
D
OUT
CLK
t
DO
V
OH
V
OL
CS
Voltage Waveforms for t
EN
1
2
3
4
B11
t
EN
Voltage Waveforms for t
DIS
D
OUT
CS
V
IH
90%
T
DIS
FIGURE 1-2:
Load Circuit for t
R
, t
F
, t
DO
.
D
OUT
Waveform 1*
D
OUT
Waveform 2†
10%
*
Waveform 1 is for an output with internal
conditions such that the output is high,
unless disabled by the output control.
†
Waveform 2 is for an output with internal
conditions such that the output is low,
unless disabled by the output control.
FIGURE 1-3:
Load circuit for t
DIS
and t
EN
.
©
2007 Microchip Technology Inc.
DS21298D-page 5
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