MC100ES6139DWR2 datasheet, PDF

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MC100ES6139DWR2: DescriptionLow Skew Clock Driver, 100E Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, PLASTIC, SOIC-20; Categorylogic logic; File Size181KB，12 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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MC100ES6139DWR2 Overview

Low Skew Clock Driver, 100E Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, PLASTIC, SOIC-20

MC100ES6139DWR2 Parametric

Parameter Name	Attribute value
Maker	Motorola ( NXP )
package instruction	PLASTIC, SOIC-20
Reach Compliance Code	unknown
Other features	ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V
series	100E
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G20
length	12.8 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	1
Number of inverted outputs
Number of terminals	20
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	0.9 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.1 ns
Maximum seat height	2.65 mm
Maximum supply voltage (Vsup)	3.8 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	ECL
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	7.5 mm

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order Number: MC100ES6139/D

Rev 0, 05/2003

Preliminary Information

2.5V/3.3V

ECL/PECL/HSTL/LVDS

÷2/4,

÷4/5/6

Clock Generation Chip

The MC100ES6139 is a low skew

÷2/4, ÷4/5/6

clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either

a differential or single--ended ECL or, if positive power supplies are used,

LVPECL input signals. In addition, by using the V

output, a sinusoidal

source can be AC coupled into the device. If a single--ended input is to be

used, the V

output should be connected to the CLK input and bypassed

to ground via a 0.01

capacitor.

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen

with an asynchronous control. The internal enable flip--flop is clocked on

the falling edge of the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock input.

Upon startup, the internal flip--flops will attain a random state; therefore,

for systems which utilize multiple ES6139s, the master reset (MR) input

must be asserted to ensure synchronization. For systems which only use

one ES6139, the MR pin need not be exercised as the internal divider

design ensures synchronization between the

÷2/4

and the

÷4/5/6

outputs

of a single device. All V

and V

pins must be externally connected to

power supply to guarantee proper operation.

The 100ES Series contains temperature compensation.

Features

•

Maximum Frequency >1.0 GHz Typical

MC100ES6139

DT SUFFIX

20 LEAD TSSOP PACKAGE

CASE 948E

DW SUFFIX

20 LEAD SOIC PACKAGE

CASE 751D

ORDERING INFORMATION

Device

MC100ES6139DT

MC100ES6139DTR2

MC100ES6139DW

MC100ES6139DWR2

Package

TSSOP-

-20

TSSOP-

-20

SO-

-20

SO-

-20

•

50 ps Output--to--Output Skew

•

PECL Mode Operating Range: V

= 2.375 V to 3.8 V

with V

= 0 V

•

ECL Mode Operating Range: V

= 0 V

with V

= --2.375 V to --3.8 V

•

Open Input Default State

Synchronous Enable/Disable

Master Reset for Synchronization of Multiple Chips

Output

LVDS and HSTL Input Compatible

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

Motorola, Inc. 2003

MC100ES6139DWR2 Related Products

	MC100ES6139DWR2	MC100ES6139DT	MC100ES6139DTR2	MC100ES6139DW
Description	Low Skew Clock Driver, 100E Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, PLASTIC, SOIC-20	Low Skew Clock Driver, 100E Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, TSSOP-20	Low Skew Clock Driver, 100E Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, TSSOP-20	Low Skew Clock Driver, 100E Series, 4 True Output(s), 0 Inverted Output(s), ECL, PDSO20, PLASTIC, SOIC-20
Maker	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )	Motorola ( NXP )
package instruction	PLASTIC, SOIC-20	TSSOP, TSSOP20,.25	TSSOP, TSSOP20,.25	PLASTIC, SOIC-20
Reach Compliance Code	unknown	unknown	unknown	unknown
Other features	ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V	ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V	ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V	ECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V
series	100E	100E	100E	100E
Input adjustment	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20
length	12.8 mm	6.5 mm	6.5 mm	12.8 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	1	1	1	1
Number of terminals	20	20	20	20
Actual output times	4	4	4	4
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	TSSOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
propagation delay (tpd)	0.9 ns	0.9 ns	0.9 ns	0.9 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.1 ns	0.1 ns	0.1 ns	0.1 ns
Maximum seat height	2.65 mm	1.2 mm	1.2 mm	2.65 mm
Maximum supply voltage (Vsup)	3.8 V	3.8 V	3.8 V	3.8 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
technology	ECL	ECL	ECL	ECL
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	7.5 mm	4.4 mm	4.4 mm	7.5 mm

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