BUP53R1 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Discrete semiconductor> The transistor> BUP53R1

BUP53R1: DescriptionPower Bipolar Transistor, 60A I(C), 250V V(BR)CEO, 1-Element, NPN, Silicon, TO-204AE, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN; CategoryDiscrete semiconductor The transistor; File Size190KB，3 Pages; ManufacturerTT Electronics plc; Websitehttp://www.ttelectronics.com/; Environmental Compliance

Download Datasheet Parametric Compare View All

BUP53R1 Overview

Power Bipolar Transistor, 60A I(C), 250V V(BR)CEO, 1-Element, NPN, Silicon, TO-204AE, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN

BUP53R1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	TT Electronics plc
package instruction	FLANGE MOUNT, O-MBFM-P2
Reach Compliance Code	compliant
ECCN code	EAR99
Shell connection	COLLECTOR
Maximum collector current (IC)	60 A
Collector-emitter maximum voltage	250 V
Configuration	SINGLE
Minimum DC current gain (hFE)	5
JEDEC-95 code	TO-204AE
JESD-30 code	O-MBFM-P2
JESD-609 code	e1
Number of components	1
Number of terminals	2
Maximum operating temperature	200 °C
Package body material	METAL
Package shape	ROUND
Package form	FLANGE MOUNT
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	NPN
Certification status	Not Qualified
surface mount	NO
Terminal surface	TIN SILVER COPPER
Terminal form	PIN/PEG
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
transistor applications	SWITCHING
Transistor component materials	SILICON

Preview

Download Datasheet

View All

SILICON MULTI-EPITAXIAL

NPN TRANSISTOR

BUP53

•

Low VCE(SAT), Fast switching.

Hermetic TO3 Metal package.

Ideally suited for Motor Control, Switching

and Linear Applications

Screening Options Available

•

ABSOLUTE MAXIMUM RATINGS

(TC = 25°C unless otherwise stated)

VCEX

VCEO

VEBO

ICM

Tstg

VBE = -1.5V

Collector – Emitter Voltage

Emitter – Base Voltage

Continuous Collector Current

Peak Collector Current

TC = 25°C

Total Power Dissipation at

Derate Above 25°C

Junction Temperature Range

Storage Temperature Range

400V

250V

10V

60A

80A

300W

1.72W/°C

-55 to +200°C

THERMAL PROPERTIES

Symbols

θJC

Parameters

Thermal Resistance, Junction To Case

Min.

Typ.

Max.

0.58

Units

°C/W

Semelab Limited reserves the right to change test conditions, parameter limits and package dimensions without notice.

Information furnished by Semelab is believed to be both accurate and reliable at the time of going to press. However

Semelab assumes no responsibility for any errors or omissions discovered in its use. Semelab encourages customers to

verify that datasheets are current before placing orders.

Semelab Limited

Coventry Road, Lutterworth, Leicestershire, LE17 4JB

Telephone +44 (0) 1455 556565

Fax +44 (0) 1455 552612

Email:

sales@semelab-tt.com

Document Number 8314

Issue 1

Page 1 of 3

Website:

http://www.semelab-tt.com

BUP53R1 Related Products

	BUP53R1	BUP53	BUP53.MOD
Description	Power Bipolar Transistor, 60A I(C), 250V V(BR)CEO, 1-Element, NPN, Silicon, TO-204AE, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN	Power Bipolar Transistor, 60A I(C), 250V V(BR)CEO, 1-Element, NPN, Silicon, TO-204AE, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN	Power Bipolar Transistor, 60A I(C), 250V V(BR)CEO, 1-Element, NPN, Silicon, TO-204AE, Metal, 2 Pin, HERMETIC SEALED, METAL, TO-3, 2 PIN
Is it Rohs certified?	conform to	incompatible	incompatible
package instruction	FLANGE MOUNT, O-MBFM-P2	HERMETIC SEALED, METAL, TO-3, 2 PIN	HERMETIC SEALED, METAL, TO-3, 2 PIN
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
Shell connection	COLLECTOR	COLLECTOR	COLLECTOR
Maximum collector current (IC)	60 A	60 A	60 A
Collector-emitter maximum voltage	250 V	250 V	250 V
Configuration	SINGLE	SINGLE	SINGLE
Minimum DC current gain (hFE)	5	5	5
JEDEC-95 code	TO-204AE	TO-204AE	TO-204AE
JESD-30 code	O-MBFM-P2	O-MBFM-P2	O-MBFM-P2
Number of components	1	1	1
Number of terminals	2	2	2
Maximum operating temperature	200 °C	200 °C	200 °C
Package body material	METAL	METAL	METAL
Package shape	ROUND	ROUND	ROUND
Package form	FLANGE MOUNT	FLANGE MOUNT	FLANGE MOUNT
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Polarity/channel type	NPN	NPN	NPN
Certification status	Not Qualified	Not Qualified	Not Qualified
surface mount	NO	NO	NO
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
transistor applications	SWITCHING	SWITCHING	SWITCHING
Transistor component materials	SILICON	SILICON	SILICON
Maker	TT Electronics plc	-	TT Electronics plc

Recommended Resources

SCA demodulator circuit diagram

Application circuit of LM1035 and 36

Common drain amplifier circuit

Electrical Principle of Huifeng Inverter Circulation Pump

Light source drive circuit

Zero-crossing pulse circuit (experimentally verified)

Newbie question: How to design a switching power supply transformer?: I just started to get in touch with switching power supplies recently. I am going to make a single-ended flyback switching power supply. After reading the information, I found that the key to the desi...; a404612303 Analogue and Mixed Signal

About SPI to I2S conversion of APB3 bus: Has anyone implemented this module? Can you give me some advice?...; zydzjy FPGA/CPLD

Wince driver interruption problem: I'm learning about interrupt drivers recently, and I don't understand a few things. I'd like to ask you guys: 1. In WinCE interrupts, the logical interrupt number is associated with an event, so how i...; fiona007 Embedded System

Verilog statement output question: input b; reg a; if(i) a = b; assign c = a; if i=0; then what is the value of c, should it be no value, or 0? c is of wire type, so it is not saved, so there is no output value, is this correct?...; tianma123 FPGA/CPLD

How to calculate the gate count of FPGA?: I often hear that FPGAs have tens of thousands of gates, but isn't the size of an FPGA measured in logic units? Is there any relationship between the two? How do you estimate tens of thousands of gate...; 心仪 FPGA/CPLD

Check out Xilinx's latest release of Targeted Design Platform domain-specific kits: Here are the pictures. It's too late, and there's nothing much to write. Just a brief explanation will suffice. If I remember anything else, I'll continue to add.This is the Spartan-6 development boar...; 凯哥 FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components