EEWORLDEEWORLDEEWORLD

Part Number

Search

531WA649M000DGR

Description
CMOS/TTL Output Clock Oscillator, 649MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531WA649M000DGR Overview

CMOS/TTL Output Clock Oscillator, 649MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531WA649M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency649 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Network connection problem using WININET under EVC4
Start a thread and use WININET to download and upload data: Some codes are as follows: int uParam = 5000; int iTimeOut = 5000, iSendTimeOut = 1000, iRecvTimeOut = 7000, iDataSendTO = 1000, iDataRecvTO...
action99 Embedded System
Recently, my boss has paid special attention to the program protection of laser equipment. Do you have any good methods?
Recently, my boss has been paying special attention to the program protection of laser equipment. Do you have any good methods to recommend?...
UP798 Embedded System
Xiao Meige will study FPGA digital tube dynamic scanning with you in depth
In electronic systems, output devices are usually required to output or display certain information to indicate the current operating status of the system. In electronic systems based on single-chip m...
小梅哥 FPGA/CPLD
What is the meaning of RAMIMAGE?
RAMIMAGE is said to be a place for OS. I think when starting OS, NK.bin should be first decompressed into a block like NK.nb0. I want to know whether RAMIMAGE is the first address of NK.bin or the fir...
mn14174 Embedded System
SensorTile.box firmware update
1. Material preparation Download collection: https://bbs.eeworld.com.cn/thread-1105280-1-1.html At present, the only information that can be downloaded seems to be here. In addition, there is a develo...
tinnu ST MEMS Sensor Creative Design Competition
What is the essential difference between PLC and RTU?
The remote module was originally designed for use in control rooms, so it has poor adaptability to harsh environments. Compared with remote modules, RTU has powerful communication functions and integr...
eeleader-mcu Industrial Control Electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 895  689  2706  1269  1959  19  14  55  26  40 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号