M368L1714DT1-CA0 datasheet, PDF

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M368L1714DT1-CA0: DescriptionDDR DRAM Module, 16MX64, 0.8ns, CMOS, DIMM-184; Categorystorage storage; File Size96KB，16 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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M368L1714DT1-CA0 Overview

DDR DRAM Module, 16MX64, 0.8ns, CMOS, DIMM-184

M368L1714DT1-CA0 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.8 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
memory density	1073741824 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Humidity sensitivity level	1
Number of functions	1
Number of ports	1
Number of terminals	184
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX64
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	225
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
self refresh	YES
Maximum standby current	0.19 A
Maximum slew rate	1.2 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

M368L1714DT1-CA0 Preview

M368L1714DT1

184pin Unbuffered DDR SDRAM MODULE

128MB DDR SDRAM MODULE

(16Mx64(8Mx16*2Bank) based on 8Mx16 DDR SDRAM)

Unbuffered 184pin DIMM

64-bit Non-ECC/Parity

Revision 0.2

May. 2002

Rev. 0.2 May. 2002

M368L1714DT1

Revision History

Revision 0 (Sep 2001)

1. First release for internal usage

184pin Unbuffered DDR SDRAM MODULE

Revision 0.1(December,2001)

- Revised "Absolute maximum rating" table in page 38.

. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V

. Changed "power dissipation" value from 8W to 12W.

- Revised AC parameter table

From

DDR266A

Min.

tHZ

tACmin

-400ps

tACmin

-400ps

0.25

10ns

Max.

tACmax

-400ps

tACmax

-400ps

DDR266B

Min.

tACmin

-400ps

tACmin

-400ps

0.25

10ns

Max.

tACmax

-400ps

tACmax

-400ps

DDR200

Min.

tACmin

-400ps

tACmin

-400ps

0.25

10ns

Max.

tACmax

-400ps

tACmax

-400ps

DDR266A

Min.

-0.75

Max.

+0.75

DDR266B

Min.

-0.75

Max.

+0.75

DDR200

Min.

-0.8

Max.

+0.8

tLZ

tWPST

(tCK)

tPDEX

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

0.4

7.5ns

0.6

0.4

7.5ns

0.6

0.4

10ns

0.6

Revision 0.2 (May 2002)

1. Change pin location of A13 from pin 103 to pin 167

Rev. 0.2 May. 2002

M368L1714DT1

184pin Unbuffered DDR SDRAM MODULE

M368L1714DT1 DDR SDRAM 184pin DIMM

16Mx64 DDR SDRAM 184pin DIMM based on 8Mx16

GENERAL DESCRIPTION

The Samsung M368L1714DT1 is 16M bit x 64 Double Data

Rate SDRAM high density memory modules based on fifth gen

of 128Mb DDR SDRAM respectively.

The Samsung M368L1714DT1 consists of eight CMOS

8M x 16 bit with 4banks Double Data Rate SDRAMs in 66pin

TSOP-II(400mil) packages mounted on a 184pin glass-epoxy

substrate. Four 0.1uF decoupling capacitors are mounted on

the printed circuit board in parallel for each DDR SDRAM.

The M368L1714DT1 is Dual In-line Memory Modules and

intended for mounting into 184pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. Data I/O transactions are possible on both

edges of DQS. Range of operating frequencies, programmable

latencies and burst lengths allow the same device to be useful

for a variety of high bandwidth, high performance memory sys-

tem applications.

FEATURE

• Performance range

Part No.

Max Freq.

Interface

M368L1714DT1-C(L)B3 167MHz(6.0ns@CL=2.5)

M368L1714DT1-C(L)A2 133MHz(7.5ns@CL=2)

M368L1714DT1-C(L)B0 133MHz(7.5ns@CL=2.5)

M368L1714DT1-C(L)A0 100MHz(10ns@CL=2)

• Power supply : Vdd: 2.5V

0.2V, Vddq: 2.5V

0.2V

SSTL_2

•

Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK )

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)

• Serial presence detect with EEPROM

• PCB :

Height 1450 (mil),

double sided component

PIN CONFIGURATIONS (Front side/back side)

Pin Front

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

/CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

Front Pin

Front

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

/CK2

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

*A12

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

Back

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

*CB4

*CB5

VDDQ

*CK0

*/CK0

VSS

*DM8

A10

*CB6

VDDQ

*CB7

KEY

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5

VSS

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

*A13

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

3 3 DQ24 63

VSS 64

3 5 DQ25 65

3 6 DQS3 66

3 8 VDD 68

3 9 DQ26 69

4 0 DQ27 70

VSS 72

4 4 *CB0 74

4 5 *CB1 75

4 6 VDD 76

4 7 *DQS8 77

4 9 *CB2 79

VSS 80

5 1 *CB3 81

BA1 82

KEY

5 3 DQ32 84

5 4 VDDQ 85

5 5 DQ33 86

5 6 DQS4 87

5 7 DQ34 88

VSS 89

BA0 90

6 0 DQ35 91

6 1 DQ40 92

PIN DESCRIPTION

Pin Name

A0 ~ A11

BA0 ~ BA1

DQ0 ~ DQ63

DQS0 ~ DQS7

CK0, CK0 , CK2, CK2

CKE0 ,CKE1

/CS0, /CS1

RAS

CAS

DM0 ~ DM7

VDD

VDDQ

VSS

VREF

VDDSPD

Function

Address input (Multiplexed)

Bank Select Address

Data input/output

Data Strobe input/output

Clock input

Clock enable input

Chip select input

Row address strobe

Column address strobe

Write enable

Data - in mask

Power supply ( 2.5V)

Power Supply for DQS (2.5V)

Ground

Power supply for reference

Serial EEPROM Power

Supply (2.3V to 3.6V)

Serial data I/O

Serial clock

Address in EEPROM

VDD identification flag

SDA

SCL

SA0 ~ 2

VDDID

No connection

* These pins are not used in this module.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.2 May. 2002

M368L1714DT1

Functional Block Diagram

CS 1

CS0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

LDQS

LDM

I/O 6

I/O 4

I/O 1

I/O 3

I/O 2

I/O 0

I/O 5

I/O 7

UDQS

UDM

I/O 8

I/O 10

I/O 15

I/O 13

I/O 12

I/O 14

I/O 11

I/O 9

UDQS

UDM

I/O 9

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 10

I/O 8

LDQS

LDM

I/O 7

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 4

I/O 6

184pin Unbuffered DDR SDRAM MODULE

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

LDQS

LDM

I/O 6

I/O 4

I/O 1

I/O 3

I/O 2

I/O 0

I/O 5

I/O 7

UDQS

UDM

I/O 8

I/O 10

I/O 15

I/O 13

I/O 12

I/O 14

I/O 11

I/O 9

UDQS

U M

I/O 9

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 10

I/O 8

LDQS

LDM

I/O 7

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 4

I/O 6

DQS0

DM0

DQ15

D 0

D 1

D 2

D 3

D 4

D 5

D 6

D 7

DQS4

DM4

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

LDQS

LDM

I/O 6

I/O 4

I/O

UDQS

UDM

I/O 9

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 10

I/O 8

LDQS

LDM

I/O 7

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 4

I/O 6

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

LDQS

LDM

I/O 6

I/O 4

I/O 1

I/O 3

I/O 2

I/O 0

I/O 5

I/O 7

UDQS

UDM

I/O 8

I/O 10

I/O 15

I/O 13

I/O 12

I/O 14

I/O 11

I/O 9

UDQS

UDM

I/O 9

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 10

I/O 8

LDQS

LDM

I/O 7

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 4

I/O 6

DQS2

DM2

DQ30

DQ31

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 5

I/O 7

UDQS

UDM

I/O 8

I/O 10

I/O 15

I/O 13

I/O 12

I/O 14

I/O 11

I/O 9

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

clock Wining

clock input

CK0/C K0

CK1/C K1

CK2/C K2

SDRAM

4 SDRAMs

Card

Edge

*Clock Net Wiring

Dram1

Dram2

R=120

Ω

Cap.

BA0 - BAN

A0 - AN

RAS

CAS

CKE0

CKE1

BA0-BAN: DDR SDRAMs D0 - D7

A0-AN: DDR SDRAMs D0 - D7

RAS: SDRAMs D0 - D7

CAS: SDRAMs D0 - D7

CKE0: SDRAMs D0 - D3

CKE1: SDRAMs D4 - D7

WE: SDRAMs D0 - D7

SA0

SA1

SA2

SCL

SDA

Cap.

Dram5

Dram6

Serial PD

DDSPD

D D

DDQ

SPD

D0 - D7

VREF

DDID

D0 - D7

Strap: see Note 4

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/ CS relationships must

be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD

≠

VDDQ.

Rev. 0.2 May. 2002

M368L1714DT1

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Voltage on V

DDQ

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

184pin Unbuffered DDR SDRAM MODULE

Symbol

, V

OUT

DDQ

STG

Value

-0.5 ~ 3.6

-1.0 ~ 3.6

-55 ~ +150

Unit

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 70°C)

Parameter

Supply voltage(for device with a nominal V

of 2.5V)

I/O Supply voltage

I/O Reference voltage

I/O Termination voltage(system)

Input logic high voltage

Input logic low voltage

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

Input crossing point voltage, CK and CK inputs

Input leakage current

Output leakage current

Output High Current(Normal strengh driver)

OUT

= V

T T

+ 0.84V

Output High Current(Normal strengh driver)

OUT

= V

T T

- 0.84V

Output High Current(Half strengh driver)

OUT

= V

T T

+ 0.45V

Output High Current(Half strengh driver)

OUT

= V

T T

- 0.45V

Symbol

DDQ

REF

I H

(DC)

I N

(DC)

I D

(DC)

O Z

Min

2.3

VDDQ/2-50mV

REF

-0.04

REF

+0.15

-0.3

0.3

1.15

-2

-5

-16.8

16.8

-9

Max

2.7

VDDQ/2+50mV

REF

+0.04

DDQ

+0.3

REF

-0.15

DDQ

+0.3

DDQ

+0.6

1.35

Unit

Note

Notes

1. Includes

25mV margin for DC offset on V

REF

, and a combined total of

50mV margin for all AC noise and DC offset on V

REF

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V

REF

and internal DRAM noise coupled

TO V

REF

, both of which may result in V

REF

noise. V

REF

should be de-coupled with an inductance of

≤

3nH.

2.V

is not applied directly to the device. V

T T

is a system supply for signal termination resistors, is expected to be set equal to

REF

, and must track variations in the DC level of V

REF

3. V

I D

is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

5. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Rev. 0.2 May. 2002

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Description	DDR DRAM Module, 16MX64, 0.8ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.7ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.7ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.8ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184	DDR DRAM Module, 16MX64, 0.75ns, CMOS, DIMM-184
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184
Contacts	184	184	184	184	184	184	184	184
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknow
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
Maximum access time	0.8 ns	0.7 ns	0.7 ns	0.75 ns	0.75 ns	0.8 ns	0.75 ns	0.75 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	100 MHz	133 MHz	133 MHz	133 MHz	133 MHz	100 MHz	133 MHz	133 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184
memory density	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bi
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	64	64	64	64	64	64	64
Humidity sensitivity level	1	1	1	1	1	1	1	1
Number of functions	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1
Number of terminals	184	184	184	184	184	184	184	184
word count	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000	16000000	16000000	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	16MX64	16MX64	16MX64	16MX64	16MX64	16MX64	16MX64	16MX64
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	225	225	225	225	225	225	225	225
power supply	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096	4096	4096	4096	4096	4096
self refresh	YES	YES	YES	YES	YES	YES	YES	YES
Maximum standby current	0.19 A	0.212 A	0.212 A	0.19 A	0.19 A	0.19 A	0.19 A	0.19 A
Maximum slew rate	1.2 mA	1.58 mA	1.58 mA	1.38 mA	1.38 mA	1.2 mA	1.38 mA	1.38 mA
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED

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