A
PPLICATION
N
OTE
A V A I L A B L E
X20C16
16K
AN56
X20C16
High Speed AUTOSTORE™ NOVRAM
2K x 8 Bit
FEATURES
DESCRIPTION
The Xicor X20C16 is a 2K x 8 NOVRAM featuring a high-
speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E
2
PROM) and the
AUTOSTORE feature which automatically saves the
RAM contents to E
2
PROM at power-down. The X20C16
is fabricated with advanced CMOS floating gate technol-
ogy to achieve high speed with low power and wide
power-supply margin. The X20C16 features a compat-
ible JEDEC approved pinout for byte-wide memories,
for industry standard RAMs, ROMs, EPROMs, and
E
2
PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E
2
PROM (store) and E
2
PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 10µs or
less. An automatic array recall operation reloads the
contents of the E
2
PROM into RAM upon power-up.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E
2
PROM, and a minimum 1,000,000 store operations to
the E
2
PROM. Data retention is specified to be greater
than 100 years.
•
•
•
•
•
•
•
Fast Access Time: 35ns, 45ns, 55ns
High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
AUTOSTORE™ NOVRAM
—Automatically Stores RAM Data Into the
E
2
PROM Array When V
CC
Low Threshold is
Detected
—User Enabled Option
—Open Drain AUTOSTORE Status Output Pin
Power-on Recall
—E
2
PROM Data Automatically Recalled Into
RAM Upon Power-up
Software Data Protection
—Locks Out Inadvertent Store Operations
Low Power CMOS
—Standby: 250
µ
A
Infinite E
2
PROM Array Recall, and RAM Read
and Write Cycles
PIN CONFIGURATION
PLASTIC
CERDIP
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
X20C16 21
20
19
18
17
16
15
VCC
WE
AS
A8
A9
TSOP
A
2
A
1
A
0
N/C
I/O
0
I/O
1
I/O
2
V
SS
V
SS
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
A
10
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LCC
PLCC
VCC
WE
NC
NE
NC
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
NC
OE
A9
A8
AS
WE
VCC
NE
NC
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X20C16
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
X20C16
4
A6
A5
A4
A3
5
6
7
8
9
10
11
12
3
2
1 32 31 30
29
28
27
26
A8
A9
NC
NC
OE
A10
CE
I/O7
I/O6
A2
A1
A0
NC
I/O0
X20C16
(TOP VIEW)
3826 FHD F02
3826 ILL F17.2
21
13
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3826 FHD F15.1
3826 FHD F03
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1991, 1995, 1996 Patents Pending
3826-2.9 7/31/97 T4/C0/D0 SH
1
Characteristics subject to change without notice
AS
25
24
23
22
NC
SOIC
A7
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
3
A
4
A
5
A
6
A
7
NC
NE
V
CC
V
CC
WE
AS
NC
A
8
A
9
NC
OE
X20C16
PIN DESCRIPTIONS
Addresses (A
0
–A
10
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of
CE, WE,
or
NE.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X20C16 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CE
or
OE
is HIGH or when
NE
is LOW.
Write Enable (WE)
The Write Enable input controls the writing of data to the
static RAM.
FUNCTIONAL DIAGRAM
Nonvolatile Enable (NE)
The Nonvolatile Enable input controls the recall function
to the E
2
PROM array.
AUTOSTORE Output (AS)
AS
is an open drain output which, when asserted indi-
cates V
CC
has fallen below the AUTOSTORE threshold
(V
ASTH
).
AS
may be wire-ORed with multiple open drain
outputs and used as an interrupt input to a microcontroller.
PIN NAMES
Symbol
A
0
–A
10
I/O
0
–I/O
7
WE
CE
OE
NE
AS
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
Nonvolatile Enable
AUTOSTORE Output
+5V
Ground
No Connect
3826 PGM T01
AS
VCC SENSE
EEPROM ARRAY
A3–A8
ROW
SELECT
CE
OE
WE
NE
A0–A2
A9–A10
CONTROL
LOGIC
COLUMN
SELECT
&
I/OS
I/O0–I/O7
3826 FHD F01
2
ST
O
HIGH SPEED
2K x 8
SRAM
ARRAY
R
R
E
EC
AL
L
X20C16
DEVICE OPERATION
The
CE, OE, WE,
and
NE
inputs control the X20C16
operation. The X20C16 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either
OE
or
CE
is HIGH, or
when
NE
is LOW.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE
and
OE
to be LOW with
WE
and
NE
HIGH. A write
operation requires
CE
and
WE
to be LOW with
NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C16.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the E
2
PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E
2
PROM array.
Recall operations are performed automatically upon
power-up and under host system control when
NE, OE
and
CE
are LOW and
WE
is HIGH. The recall operation
takes a maximum of 5µs.
SDP (Software Data Protection)
There are two methods of initiating a store operation.
The first is the software store command. This command
takes the place of the hardware store employed on the
X20C04. This command is issued by entering into the
special command mode:
NE, CE,
and
WE
strobe LOW
while at the same time a specific address and data
combination is sent to the device. This is a three step
operation: the first address/data combination is 555[H]/
AA[H]; the second combination is 2AA[H]/55[H]; and the
final command combination is 555[H]/33[H]. This se-
quence of pseudo write operations will immediately
initiate a store operation. Refer to the software com-
mand timing diagrams for details on set and hold times
for the various signals.
The second method of storing data is with the
AUTOSTORE command. When enabled, data is auto-
matically stored from the RAM into the E
2
PROM array
whenever V
CC
falls below the preset Autostore thresh-
old. This feature is enabled by performing the first two
steps for the software store with the command combina-
tion being 555[H]/CC[H].
The AUTOSTORE feature is disabled by issuing the
three step command sequence with the command com-
bination being 555[H]/CD[H]. The AUTOSTORE feature
will also be reset if V
CC
falls below the power-up reset
threshold (approximately 3.5V) and is then raised back
into the operation range.
Write Protection
The X20C16 supports two methods of protecting the
nonvolatile data.
—If after power-up the AUTOSTORE feature is not
enabled, no AUTOSTORE can occur.
—V
CC
Sense – All functions are inhibited when V
CC
is
≤
3.0V typical.
SYMBOL TABLE
The following symbol table provides a key to under-
standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
3
X20C16
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS .......................................
–1V to +7V
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds) ...... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Military
Min.
0°C
–40°C
–55°C
Max.
+70°C
+85°C
+125°C
3826 PGM T02.1
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any conditions other than those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Supply Voltage
X20C16
Limits
5V
±10%
3826 PGM T03.1
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
l
CC1
Parameter
V
CC
Current (Active)
Min.
Max.
100
Units
mA
Test Conditions
NE
=
WE
= V
IH
,
CE
=
OE
= V
IL
Address Inputs = 0.4V/2.4V Levels
@ f = 20MHz All I/Os = Open
All Inputs = V
IH
All I/Os = Open
CE
= V
IH,
All Other Inputs = V
IH
All I/Os = Open
All Inputs = V
CC
– 0.3V
All I/Os = Open
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
,
CE
= V
IH
I
CC2
I
CC3(2)
I
SB1
I
SB2
I
LI
I
LO
V
IL(1)
V
IH(1)
V
OL
V
OLAS
V
OH
V
CC
Current During Store
V
CC
Current During
AUTOSTORE
V
CC
Standby Current
(TTL Input)
V
CC
Standby Current
(CMOS Input)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
AUTOSTORE Output
Output HIGH Voltage
5
2.5
10
250
10
10
0.8
V
CC
+ 0.5
0.4
0.4
mA
mA
mA
µA
µA
µA
V
V
V
V
V
–1
2
2.4
I
OL
= 4mA
I
OLAS
= 1mA
I
OH
= –4mA
3826 PGM T04.3
POWER-UP TIMING
Symbol
t
PUR(2)
t
PUW(2)
Parameter
Power-Up to RAM Operation
Power-Up to Nonvolatile Operation
Max.
100
5
Units
µs
ms
3826 PGM T05
CAPACITANCE
T
A
= +25°C, f = 1MHz, V
CC
= 5V.
Symbol
C
I/O(2)
C
IN(2)
Test
Input/Output Capacitance
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
3826 PGM T06.1
Notes:
(1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
4
X20C16
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Store Cycles
Data Retention
MODE SELECTION
CE
H
L
L
L
L
L
L
L
L
WE
X
H
L
L
H
L
H
L
H
NE
X
H
H
H
L
L
H
L
L
OE
X
L
H
H
L
H
H
L
H
Mode
Not Selected
Read RAM
Write “1” RAM
Write “0” RAM
Array Recall
Software Command
Output Disabled
Not Allowed
No Operation
I/O
Output High Z
Output Data
Input Data High
Input Data Low
Output High Z
Input Data
Output High Z
Output High Z
Output High Z
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
3826 PGM T09
Min.
100,000
1,000,000
100
Units
Data Changes Per Bit
Store Cycles
Years
3826 PGM T07.1
EQUIVALENT A.C. LOAD CIRCUIT
5V
735Ω
OUTPUT
318Ω
30pF
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
0V to 3V
5ns
1.5V
3826 PGM T08.1
3826 FHD F04
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
