K7A163609A
K7A163209A
K7A161809A
PRELIMINARY
512Kx36/x32 & 1Mx18 Synchronous SRAM
512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
V
DD
= 3.3V +0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Con-
tention only for TQFP ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC , ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
• Operating in commeical and industrial temperature range.
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GENERAL DESCRIPTION
The K7A163609A, K7A163209A and K7A161809A are
18,874,368-bit Synchronous Static Random Access Mem-
ory designed for high performance second level cache of
Pentium and Power PC based System.
It is organized as 512K(1M) words of 36(32/18) bits and
integrates address and control registers, a 2-bit burst
address counter and added some new functions for high
performance cache RAM applications; GW, BW , LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache control-
ler(ADSC) inputs. Subsequent burst addresses are gener-
ated internally in the system′s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst
sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A163609A, K7A163209A and K7A161809A are fab-
ricated using SAMSUNG′s high performance CMOS tech-
nology and is available in a 100pin TQFP, 119BGA and
165FBGA package. Multiple power and ground pins are
utilized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-25
4.0
2.6
2.6
-22
4.4
2.8
2.8
-20
5.0
3.1
3.1
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
BURST CONTROL
BURST
ADDRESS
COUNTER
512Kx36/32 , 1Mx18
MEMORY
ARRAY
CONTROL
REGISTER
ADV
ADSC
LOGIC
A′
0
~A′
1
A
0
~A
1
A
0
~A
18
or A
0
~A
19
ADDRESS
REGISTER
A
2
~A
18
or A
2
~A
19
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
DQPa ~ DQPd
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
-3-
Aug 2001
Rev 0.2
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