SGRAM MODULE
KMM965G511AQ(P)N / KMM966G511AQ(P)N
KMM965G511AQ(P)N / KMM966G511AQ(P)N SGRAM SODIMM
512Kx64 SGRAM SODIMM based on 512Kx32, 2K Refresh, 3.3V Synchronous Graphic RAMs
GENERAL DESCRIPTION
The Samsung KMM965(6)G511AQ(P)N is a 512K bit x 64
Synchronous Graphic RAM high density memory module. The
Samsung KMM965(6)G511AQ(P)N consists of two CMOS
512K x 32 bit Synchronous Graphic RAMs in 100pin QFP
packages mounted on a 144pin glass-epoxy substrate. Five
0.1uF decoupling capacitors are mounted on the printed
circuit
board
for
each
Synchronous
GRAM.
The
KMM965(6)G511AQ(P)N is a Small Outline Dual In-line Mem-
ory Module and is intended for mounting into 144-pin edge
connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
•
•
•
•
•
•
•
FEATURE
• Performance range
Part NO.
KMM965G511AQ(P)N-G5
KMM965G511AQ(P)N-G6
KMM965G511AQ(P)N-G7
KMM965G511AQ(P)N-G8
Max. Freq. (t
CC
)
200MHz (5ns) @CL=3
166MHz (6ns) @CL=3
143MHz (7ns) @CL=3
125MHz (8ns) @CL=3
* KM965G511AQN : based on PQFP Component
KM965G511APN : based on TQFP Component
Burst Mode Operation
BLOCK-WRITE and Write-per-bit capability
Independent byte operation via DQM0 ~ 7
Auto & Self Refresh Capability (2048 cycles / 32ms)
LVTTL compatible inputs and outputs
Single 3.3V±0.3V power supply
MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
• Optional Serial PD with EEPROM (KMM966G511A)
• Resistor Strapping Options for speed and CAS Latency
• PCB : Height(1000mil), single sided components
PIN CONFIGURATIONS (Front Side / Back Side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
SS
DQ63
DQ61
DQ59
DQ57
V
DD
DQ55
DQ53
DQ51
DQ49
V
SS
DQM7
DQM5
V
DD
DQ47
DQ45
DQ43
DQ41
V
SS
DQ39
DQ37
DQ35
DQ33
V
DD
RSVD
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ62
DQ60
DQ58
DQ56
V
DD
DQ54
DQ52
DQ50
DQ48
V
SS
DQM6
DQM4
V
DD
DQ46
DQ44
DQ42
DQ40
V
SS
DQ38
DQ36
DQ34
DQ32
V
DD
RSVD
Pin
Front
Pin
Back
Pin
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ31
DQ29
DQ27
DQ25
V
SS
DQ23
DQ21
DQ19
DQ17
V
DD
DQM3
DQM1
V
SS
DQ15
DQ13
DQ11
DQ9
V
DD
DQ7
DQ5
DQ3
DQ1
V
SS
**SDA
V
DD
Pin
Back
PIN NAMES
Pin Name
A0 ~ A9
BA(A10)
DQ0 ~ 63
CKE
CS0, *CS1
RAS
CAS
WE
DSF
DQM0 ~ 7
V
DD
V
SS
**SDA
**SBA
**SCL
RSVD
RFU
NC
Function
Address Input(multiplexed)
Bank Select Address
Data Input / Output
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Define Special Function
DQM
Power Supply (3.3V)
Ground
Serial Address Data I/O
EEPROM Device Address
Serial Clock
Reserved
Reserved for future use
No Connection
96 DQ30
98 DQ28
100 DQ26
102 DQ24
104
V
SS
106 DQ22
108 DQ20
110 DQ18
112 DQ16
114
V
DD
116 DQM2
118 DQM0
120
V
SS
122 DQ14
124 DQ12
126 DQ10
128 DQ8
130
V
DD
132 DQ6
134 DQ4
136 DQ2
138 DQ0
140
V
SS
142 **SCL
144
V
DD
Voltage Key
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
RSVD
RSVD
V
SS
DSF
RFU
RFU
V
DD
CS1
RAS
WE
V
SS
CLK1
V
DD
RSVD
RSVD
(A11)
BA(A10)
A7
V
SS
A5
A3
A1
V
DD
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
RSVD
RSVD
V
SS
RFU
RFU
**SBA
V
DD
CS0
CAS
CKE
V
SS
CLK0
V
DD
RSVD
A8
A9/AP
A6
V
SS
A4
A2
A0
V
DD
CLK0, *CLK1 Clock Input
*
These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
-3-
Rev. 0.0 (Jul. 1999)
SGRAM MODULE
Pin
CLK
CS
Name
System Clock
Chip Select
KMM965G511AQ(P)N / KMM966G511AQ(P)N
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t
SS
prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA9, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power and ground for the input buffers and the core logic.
PIN CONFIGURATION DESCRIPTION
CKE
Clock Enable
A0 ~ A9
BA(A10)
RAS
CAS
WE
DQM0 ~ 7
DQ0 ~ 63
DSF
V
DD
/V
SS
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply/Ground
RESISTOR STRAPPING OPTIONS
Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information
for each clock frequency is indicated in the section titled
AC CHARATERISTICS.
Clock Frequency and Memory Timing
Cycle Time
8ns
7ns
6ns
5ns
DQ30
1
1
0
0
DQ29
0
1
0
1
CAS Latency
CAS Latency
3
2 and 3
DQ31
0
1
-4-
Rev. 0.0 (Jul. 1999)
MCU
京公网安备 11010802033920号
EEWORLD
