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ILDP-67205V-65

Description
FIFO, 8KX9, 65ns, Asynchronous, CMOS, PDFP28, 0.400 INCH, FP-28
Categorystorage    storage   
File Size144KB,15 Pages
ManufacturerTEMIC
Websitehttp://www.temic.de/
Download Datasheet Parametric View All

ILDP-67205V-65 Overview

FIFO, 8KX9, 65ns, Asynchronous, CMOS, PDFP28, 0.400 INCH, FP-28

ILDP-67205V-65 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerTEMIC
package instruction0.400 INCH, FP-28
Reach Compliance Codeunknown
Maximum access time65 ns
Maximum clock frequency (fCLK)12.5 MHz
period time80 ns
JESD-30 codeR-PDFP-F28
JESD-609 codee0
memory density73728 bit
Memory IC TypeOTHER FIFO
memory width9
Number of functions1
Number of terminals28
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX9
ExportableNO
Package body materialPLASTIC/EPOXY
encapsulated codeDFP
Encapsulate equivalent codeFL28,.4
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.00004 A
Maximum slew rate0.07 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
MATRA MHS
L 67205
8K
×
9 / 3.3 Volts CMOS Parallel FIFO
Introduction
The L67205 implements a first-in first-out algorithm,
featuring asynchronous read/write operations. The FULL
and EMPTY flags prevent data overflow and underflow.
The Expansion logic allows unlimited expansion in word
size and depth with no timing penalties. Twin address
pointers automatically generate internal read and write
addresses, and no external address information are
required for the MHS FIFOs. Address pointers are
automatically incremented with the write pin and read
pin. The 9 bits wide data are used in data communications
applications where a parity bit for error checking is
necessary. The Retransmit pin reset the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Using an array of eigh transistors (8 T) memory cell and
fabricated with the state of the art 1.0
µm
lithography
named SCMOS, the L 67205 combine an extremely low
standby supply current (typ = 1.0
µA)
with a fast access
time at 55 ns over the full temperature range. All versions
offer battery backup data retention capability with a
typical power consumption at less than 5
µW.
For military/space applications that demand superior
levels of performance and reliability the L 67205 is
processed according to the methods of the latest revision
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
Features
D
D
D
D
First-in first-out dual port memory
Single supply 3.3
±
0.3 volts
8192
×
9 organisation
Fast access time
55, 60, 65 ns, commercial, industrial military
and automotive
D
Wide temperature range :
– 55
°C
to + 125
°C
D
67205L low power
67205V very low power
D
D
D
D
D
D
D
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation 2 V data retention
High performance SCMOS technology
Rev. C (10/11/94)
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