19-5747; Rev 1; 2/11
DS26900
JTAG Multiplexer/Switch
General Description
The DS26900 is a JTAG signal multiplexer providing
connectivity between one of three master ports and
up to 18 (36 in cascade configuration) secondary
ports. The device is fully configurable from any one of
the three master ports. The DS26900 can
automatically detect the presence JTAG devices on
the secondary ports.
The DS26900 can be used in multiple configurations
including as a single device, two cascaded devices,
or two redundant devices.
All device control and configuration is accomplished
through standard JTAG operations via the selected
master port.
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Features
Efficient Solution for Star Architecture JTAG
Provides Transparent Communications
Between the Arbitrated Master and a Selected
Secondary Port
Single-Package Solution Provides 18
Secondary Ports
Two-Package Cascade Configuration
Provides 36 Secondary Ports
Three Arbitrated Master Ports
Autodetection of Port Presence
Internal Pullup/Down Resistors
Two 32-Bit Scratchpad Registers
Four GPIO Pins for Read/Write Control and
Signaling Applications
Operation Up to 50MHz
Signal Path Modification Options
Redundancy with High-Impedance Pin
Independent Periphery JTAG
Configuration Mode Uses IEEE 1149.1 TAP
Controller
Supports Live Insertion/Withdrawal
3.3V Operation
Industrial Temperature Operation
RoHS-Compliant Packaging
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Applications
MicroTCA® Chassis
ATCA® Chassis
AMC Carrier Cards
JSM Modules
System Level JTAG
MicroTCA JSM Functional Diagram
AMC1
AMC2
DS26900
JTAG
SWITCH
MCH1
MASTER3
MCH2
MASTER2
AMC3
AMC4
AMCn
AMC18
PART
DS26900LN+
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
144 LQFP
CRAFT
MASTER1
+Denotes
a lead(Pb)-free/RoHS-compliant package.
MicroTCA and ATCA are registered trademarks of PICMG.
______________________________________________
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
__________________________________________________________________________________________DS26900
Table of Contents
1.
2.
3.
4.
4.1
BLOCK DIAGRAM ........................................................................................................................ 6
PIN DESCRIPTIONS ..................................................................................................................... 7
FUNCTIONAL DESCRIPTION .................................................................................................... 19
DETAILED DESCRIPTION.......................................................................................................... 20
M
ODES OF
O
PERATION
............................................................................................................... 20
Single-Package Mode ..................................................................................................................... 20
Cascade Configuration Modes ........................................................................................................ 21
Deselect Mode and Redundancy..................................................................................................... 22
Missing Test Master or Unused Test Master Port ............................................................................ 24
Detection of the Presence of Secondary Ports................................................................................. 24
Selection of the Secondary Port ...................................................................................................... 24
Master Port/Secondary Port Path Timing Description ...................................................................... 24
4.1.1
4.1.2
4.1.3
4.2
M
ASTER
A
RBITRATION
................................................................................................................ 23
4.2.1
4.2.2
4.2.3
4.2.4
4.3
4.4
4.5
4.6
4.7
5.
5.1
5.2
6.
6.1
7.
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
GPIO P
INS
—G
ENERAL
-P
URPOSE
I/O ......................................................................................... 25
P
ROGRAMMABLE
P
ULLUP
/P
ULLDOWN
R
ESISTORS
........................................................................ 25
S
IGNAL
P
ATH
C
ONFIGURATION
—I
NVERSIONS
.............................................................................. 25
S
WITCH
C
ONFIGURATION BY
E
XTERNAL
T
EST
M
ASTER
................................................................. 25
S
WITCH
C
ONFIGURATION BY
T
EST
M
ASTER
1
OR
T
EST
M
ASTER
2................................................. 26
RESETS ...................................................................................................................................... 27
G
LOBAL
R
ESET
U
SAGE
............................................................................................................... 27
S
ECONDARY
P
ORT
R
ESETS
........................................................................................................ 27
CONFIGURATION MODE ........................................................................................................... 28
S
WITCH
TAP C
ONTROLLER
......................................................................................................... 28
Switch Instructions .......................................................................................................................... 28
6.1.1
DEVICE REGISTERS .................................................................................................................. 31
ADDITIONAL APPLICATION INFORMATION ............................................................................ 37
A
CCESSING
I
NDIVIDUAL
D
EVICE
JTAG
ON A
B
OARD
..................................................................... 37
U
SING
LED I
NDICATORS ON THE
SSPI, ACT
AND
MCI
P
INS
.......................................................... 37
U
SING
2.7V
AND
1.8V L
OGIC
L
EVELS WITH THE
DS26900 ............................................................ 37
S
ERIES
T
ERMINATION
R
ESISTORS
............................................................................................... 37
PERIPHERY JTAG...................................................................................................................... 38
P
ERIPHERY
JTAG D
ESCRIPTION
................................................................................................. 38
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
............................................................. 39
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
...................................................................... 41
SAMPLE/PRELOAD ....................................................................................................................... 41
EXTEST ......................................................................................................................................... 41
BYPASS ......................................................................................................................................... 41
IDCODE ......................................................................................................................................... 41
HIGHZ ............................................................................................................................................ 41
CLAMP ........................................................................................................................................... 42
Bypass Register.............................................................................................................................. 42
Identification Register...................................................................................................................... 42
Boundary Scan Register ................................................................................................................. 42
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
JTAG T
EST
R
EGISTERS
.............................................................................................................. 42
9.4.1
9.4.2
9.4.3
2
__________________________________________________________________________________________DS26900
10.
OPERATING PARAMETERS...................................................................................................... 43
T
HERMAL
I
NFORMATION
........................................................................................................... 43
DC C
HARACTERISTICS
............................................................................................................ 43
10.1
10.2
11.
AC TIMING .................................................................................................................................. 44
11.1
S
WITCH
TAP C
ONTROLLER
I
NTERFACE
T
IMING
......................................................................... 44
11.2
T
RANSPARENT
M
ODE
M
ASTER
/S
LAVE
P
ORT
T
IMING
................................................................. 45
11.3
P
ERIPHERY
JTAG I
NTERFACE
T
IMING
...................................................................................... 46
12. PIN CONFIGURATION ................................................................................................................ 47
13.
14.
PACKAGE INFORMATION ......................................................................................................... 48
DOCUMENT REVISION HISTORY ............................................................................................. 49
3
__________________________________________________________________________________________DS26900
List of Figures
Figure 1-1. DS26900 Block Diagram ...................................................................................................................... 6
Figure 4-1. Configuration for 3 Masters, 18 Secondary Ports ................................................................................ 20
Figure 4-2. Configuration for 1 Master, 20 Secondary Ports.................................................................................. 20
Figure 4-3. Two Cascaded Devices...................................................................................................................... 21
Figure 4-4. Three Cascaded Devices Using External Select Logic........................................................................ 22
Figure 9-1. Periphery JTAG Block Diagram .......................................................................................................... 38
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................. 39
Figure 11-1. Switch TAP Controller Interface Timing Diagram .............................................................................. 44
Figure 11-2. Transparent Mode Master/Slave Port Timing Diagram ...................................................................... 45
Figure 11-3. Periphery JTAG Interface Timing Diagram ....................................................................................... 46
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__________________________________________________________________________________________DS26900
List of Tables
Table 2-1. Pin Descriptions (Sorted by Function).................................................................................................... 7
Table 2-2. Pin Description (Sorted by Pin Number) .............................................................................................. 13
Table 4-1. Mode Pins ........................................................................................................................................... 20
Table 4-2. Master Arbitration ................................................................................................................................ 23
Table 4-3.
ACT
Output States .............................................................................................................................. 24
Table 6-1. Switch TAP Instruction Codes ............................................................................................................. 28
Table 7-1. DS26900 List of Registers ................................................................................................................... 31
Table 7-2. Secondary Port Selection Bits and Indicator Pins................................................................................. 35
Table 9-1. Periphery JTAG Instruction Codes....................................................................................................... 41
Table 10-1. Thermal Characteristics..................................................................................................................... 43
Table 10-2. Recommended DC Operating Conditions .......................................................................................... 43
Table 10-3. DC Electrical Characteristics ............................................................................................................. 43
Table 11-1. Switch TAP Controller Interface Timing ............................................................................................. 44
Table 11-2. Master/Slave Port Timing .................................................................................................................. 45
Table 11-3. Periphery JTAG Interface Timing....................................................................................................... 46
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