TSC21020F-20MBHXXX datasheet, PDF - EEWORLD Datasheet

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TSC21020F-20MBHXXX: DescriptionFloating Point Processor, 40-Bit, CMOS, CQFP256, CERAMIC, MQFP-256; CategoryThe embedded processor and controller Microcontrollers and processors; File Size484KB，37 Pages; ManufacturerAtmel (Microchip)

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TSC21020F-20MBHXXX Overview

Floating Point Processor, 40-Bit, CMOS, CQFP256, CERAMIC, MQFP-256

TSC21020F-20MBHXXX Parametric

Parameter Name	Attribute value
Maker	Atmel (Microchip)
Parts packaging code	QFP
package instruction	QFF,
Contacts	256
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	40
JESD-30 code	S-CQFP-F256
length	37.085 mm
low power mode	NO
Number of terminals	256
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output data bus width	40
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Maximum seat height	3.18 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	FLAT
Terminal pitch	0.508 mm
Terminal location	QUAD
total dose	100k Rad(Si) V
width	37.085 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, FLOATING POINT PROCESSOR

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TSC21020F

Radiation Tolerant 32/40–Bit IEEE Floating–Point

DSP Microprocessor

Introduction

Atmel is manufacturing a radiation tolerant version of the

Analog Devices ADSP–21020 32/40–Bit Floating–Point

DSP.

The product is pin and code compatible with ADI

product, making system development straight forward

and cost effective, using existing development tools and

algorithms.

Features

D

Superscalar IEEE Floating-Point-Processor

D

Off-Chip Harvard Architecture Maximizes Signal Processing

Performance

D

50 ns, 20 MIPS Instruction Rate, Single-Cycle Execution

D

60 MFLOPS Peak, 40 MFLOPS Sustained Performance

D

1024-Point Complex FFT Benchmark : 0.975 ms

D

Divide (y/x) : 300 ns

D

Inverse Square Root (1/√x) : 450 ns

D

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats

D

32-Bit Fixed-Point Formats, Integer and Fractional, with

80-Bit Accumulators

D

IEEE Exception Handling with Interrupt on Exception

D

Three Independent Computation Units : Multiplier, ALU,

and Barrel Shifter

D

Dual Data Address Generators with Indirect, Immediate,

Modulo, and Bit Reverse Addressing Modes

D

Two Off-Chip Memory Transfers in Parallel with Instruction

Fetch and Single-Cycle Multiply & ALU Operations

D

Multiply with Add & Subtract for FFT Butterfly

Computation

D

Efficient Program Sequencing with Zero-Overhead

Looping : Single-Cycle Loop Setup

D

Single-Cycle Register File Context Switch

D

23 ns External RAM Access Time for Zero-Wait-State, 40 ns

Instruction Execution

D

IEEE JTAG Standard 1149.1 Test Access Port and On-Chip

Emulation Circuitry

D

223 CPGA package for breadboarding

D

256 Multi layer quad flat pack, flat leads, for flight models

D

Full compatible with Analog Devices ADSP-21020

D

Latch up immune

D

Total dose better than 100 Krad (Si)

D

SEU immunity better than 50 MeV/mg/cm

2

D

For 25 MHz specification, call factory

– Design using patent from INPG–CNRS Denis BESSOT / Raoul VELAZCO

– Product licensed from Analog Devices Inc.

1

Rev. E – Oct. 05, 1998

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