Freescale Semiconductor
Technical Data
Document order number:
MC33480
Rev 2.0, 1/2006
Smart Front Corner Light
Switch (Triple 10 mΩ and Dual
35 mΩ)
The 33480 is designed for low-voltage automotive and industrial
lighting applications. Its five low R
DS(ON)
MOSFETs (three 10 mΩ,
two 35 mΩ) can control the high sides of five separate resistive loads
(bulbs).
Programming, control, and diagnostics are accomplished using a
16-bit SPI interface. Each output has its own PWM control via SPI.
The 33480 has highly sophisticated failure mode handling to provide
high availability of the outputs. Its multiphase control and output edge
shaping improves electromagnetic compatibility (EMC) behavior.
The 33480 is packaged in a power-enhanced 12 x 12 nonleaded
Power QFN package with exposed tabs.
Features
•
•
•
•
•
•
•
•
•
•
•
Triple 10 mΩ and Dual 35 mΩ High-Side Switches
16-bit SPI Communication Interface with Daisy Chain Capability
Current Sense Output with SPI-Programmable Multiplex Switch
Digital Diagnosis Feature
PWM Module with Multiphase Feature
Fully Protected Switches
Overcurrent Shutdown detection
Power Net and Reverse Polarity Protection
Low-Power Mode
Fail Mode Functions including Autorestart feature
External smart power switch control including current recopy
33480
HIGH-SIDE SWITCH
Bottom View
PNASUFFIX
98ARL10596D
24-TERMINAL PQFN
ORDERING INFORMATION
Device
PC33480PNA/R2
Temperature
Range (T
A
)
-40°C to 125°C
Package
24 PQFN
12 V
5.0 V
12 V
33480
VCC
LIMP
FLASHER
IGN
RSTB
CLOCK
CS
SO
SI
SCLK
CSNS
GND
OUT3
OUT4
OUT5
FETIN
FETOUT
Smart
Switch
VBAT
CP
OUT1
OUT2
Watchdog
MCU
Figure 1. 33480 Simplified Application DiagraM
* This document contains information on a product under development.
Freescale reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
Vcc failure
detection
I
UP
Internal
Regulator
VBAT
OV/UV/POR
detections
CP
Charge Pump
CS
SO
SI
SCLK
I
DWN
SPI
3.0 MHz
PWM
Module
Logic
Gate Drive
drain/gate clamp
OUT1
Overcurrent
Detection
Open Load
Detection
Overtemperature
Detection
CLOCK
LIMP
FLASHER
IGN
RSTB
(fault ma-
nagement)
OUT1
I
DWN
R
DWN
OUT2
OUT2
Overtemperature
Prewarning
OUT3
OUT3
OUT4
OUT4
OUT5
Selectable Output Current
Recopy (Analog MUX)
Vcc
OUT5
CSNS
FETIN
Driver for External
MOSFET
FETOUT
GND
Figure 2. 33480 Simplified Internal Block Diagram
33480
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
FLASHER
FETOUT
CLOCK
RSTB
SCLK
LIMP
V
CC
13 12 11 10
CP
GND
16
17
9
8
7
6
5
4
3
IGN
2
SO
NC
CS
SI
24
14
GND
23
FETIN
1
CSNS
GND
22
OUT1
Definition
OUT5
18
15
VBAT
19
OUT4
20
OUT3
21
OUT2
Figure 3. 33480 Terminal Connections (Transparent Top View Of Package)
Table 1. 33480 Terminal Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on
Page 17.
Terminal
Number
1
2
3
Terminal
Name
FETIN
IGN
RSTB
Terminal
Function
Input
Input
Input
Formal Name
External FET Input
Ignition Input
(Active High)
Reset
This terminal is the current sense recopy of the external SMART MOSFET.
This input wakes the device. It also controls the Outputs 1 and 2 in case of Fail
mode activation. This terminal has a passive internal pulldown.
This input wakes the device. It is also used to initialize the device configuration
and fault registers through SPI. This digital terminal has a passive internal
pulldown.
This input wakes the device. The Fail mode can be activated by this digital input.
This terminal has a passive internal pulldown.
The PWM frequency and timing are generated from this digital clock input by
the PWM module. This terminal has an active internal pulldown current source.
The Fail mode can be activated by this digital input. This terminal has an active
internal pulldown current source.
No internal connection to this terminal.
When this digital signal is high, SPI signals are ignored. Asserting this terminal
low starts an SPI transaction. The transaction is signaled as completed when
this signal returns high. This terminal has an active internal pullup current
source.
This digital input terminal is connected to the master microcontroller providing
the required bit shift clock for SPI communication. This terminal has an active
internal pulldown current source.
4
5
6
7
8
FLASHER
CLOCK
LIMP
NC
CS
Input
Input
Input
NC
Input
Flasher Input
(Active High)
Clock Input
Limp Home Input
(Active High)
No Connect
Chip Select
(Active Low)
9
SCLK
Input
SPI Clock Input
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TERMINAL CONNECTIONS
Table 1. 33480 Terminal Definitions (continued)
A functional description of each terminal can be found in the Functional Terminal Description section beginning on
Page 17.
Terminal
Number
10
11
12
13
14,17,23
15
16
18
22
19
20
21
24
Terminal
Name
SI
VCC
Terminal
Function
Input
Power
Output
Output
Ground
Power
Output
Output
Formal Name
Master-Out Slave-
In
Logic Supply
Master-In Slave-
Out
External FET Gate
Ground
Battery Input
Charge Pump
Output 1
Output 5
Output 2
Output 3
Output 4
Current Sense
Output
Definition
This data input is sampled on the positive edge of the SCLK. This terminal has
an active internal pulldown current source.
SPI Logic power supply.
SPI data is sent to the MCU by this terminal. This data output changes on the
negative edge of SCLK and when
CS
is high, this terminal is high impedance.
This terminal controls an external SMART MOSFET by logic level. This output
is also called OUT6.
This terminal is the ground for the logic and analog circuitry of the device
(1)
.
Power supply terminal.
This terminal is the connection for an external tank capacitor (for internal use
only).
Protected 35 mΩ high-side power output to the load.
SO
FETOUT
GND
VBAT
CP
OUT1
OUT5
OUT2
OUT3
OUT4
CSNS
Output
Protected 10 mΩ high-side power output to the load.
Output
This terminal is used to output a current proportional to OUT1:OUT5, FET in
current, and it is used externally to generate a ground-referenced voltage for the
microcontroller to monitor output current. OUT1:OUT5 and FET in choice is SPI
programmable.
Notes
1. The pins 14, 17 and 23 must be shorted on the board.
33480
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
Overvoltage Test Range (all OUT[1:5] ON with nominal DC current)
2.0 Hours @ 25°C
1.0 Min @ 25°C
Load Dump (400 ms) @ 25°C
Reverse Polarity Voltage Range (all OUT[1:5] ON with nominal DC current)
2.0 Min @ 25°C
V
CC
Supply Voltage
OUT[1:5] Voltage
Positive
Negative (ground disconnected)
Digital Input Current in Clamping Mode (SI, SCLK,
CS
, IGN, FLASHER, LIMP)
SO and FETOUT Outputs Voltage
FET in Input Current
Outputs clamp energy using single pulse method (L=2mH; R=0; Vbat=14V
@150°C initial)
OUT[1,5]
OUT[2:4]
ESD Voltage
(2)
Human Body Model (HBM)
Human Body Model (HBM) OUT [1:5]
Charge Device Model (CDM)
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Peak Terminal Re-flow Temperature During Solder Mounting
(3)
Storage Temperature
THERMAL RESISTANCE
Thermal Resistance, Junction to Case
(4)
R
θ
JC
1.0
T
A
T
J
T
SOLDER
T
STG
- 40 to 125
- 40 to 150
260
- 55 to 150
°C
E
1,5
E
2,3,4
V
ESD
±2kV
±8kV
TBD
85
300
V
I
IN
V
SO
I
FET
in
V
CC
V
OUT
40
-16
5.0
- 0.3 to V
CC
+ 0.3
10
mA
V
mA
V
BAT
- 15
-0.3 to 5.5
V
V
V
BAT
20
27
40
V
V
Symbol
Value
Unit
mJ
°
C
°
C
°
K/W
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω)
and the Charge Device
Model.
3. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device. If the qualification fails, T
SOLDER
will be changed for 240°C.
4.
Typical value guaranteed per design.
33480
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
京公网安备 11010802033920号
EEWORLD
