Freescale Semiconductor
Advance Information
Document Number: MC33981
Rev. 8.0, 6/2009
Single High Side Switch (4.0 mΩ),
PWM clock up to 60 kHz
The 33981 is a high frequency, self-protected 4.0 mΩ R
DS(ON)
high
side switch used to replace electromechanical relays, fuses, and
discrete devices in power management applications.
The 33981 can be controlled by Pulse-width Modulation (PWM) with
a frequency up to 60 kHz. It is designed for harsh environments, and it
includes self-recovery features. The 33981 is suitable for loads with high
inrush current, as well as motors and all types of resistive and inductive
loads.
The 33981 is packaged in a 12 x 12 non-leaded power-enhanced
Power QFN package with exposed tabs.
Features
• Single 4.0 mΩ R
DS(ON)
maximum high side switch
• PWm capability up to 60 kHz with duty cycle from 5% to 100%
• Very low standby current
• Slew rate control with external capacitor
• Over-current and over-temperature protection, under-voltage
shutdown and fault reporting
• Reverse battery protection
• Gate drive signal for external low side N-channel MOSFET with
protection features
• Output current monitoring
• Temperature feedback
• Pb-free packaging designated by suffix code PNA
33981
HIGH SIDE SWITCH
Bottom View
PNA (Pb-Free Suffix)
98ARL10521D
16-PIN PQFN (12 X 12)
ORDERING INFORMATION
Device
MC33981BPNA/R2
Temperature
Range (T
A
)
- 40°C to 125°C
Package
16 PQFN
V
DD
V
DD
V
PWR
33981
CONF
I/O
I/O
VPWR
CBOOT
OUT
DLS
FS
INLS
EN
INHS
TEMP
CSNS
MCU
I/O
I/O
A/D
A/D
GLS
OCLS SR GND
M
Figure 1. 33981 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007 - 2008. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
Under-voltage
Detection
TEMP
Temperature
Feedback
Bootstrap Supply
CBOOT
SR
FS
EN
INHS
INLS
Logic
Current Protection
Gate Driver
Slew Rate Control
OUT
Over-temperature
Detection
5.0V
R
DWN
I
CONF
I
DWN
Cross-
Conduction
OUT Current
Recopy
Low Side
5.0 V
Gate Driver
and Protection
GLS
DLS
CONF
I
OCLS
GND
CSNS
OCLS
Figure 2. 33981 Simplified Internal Block Diagram
33981
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
Package Transparent Top View
CSNS
TEMP
EN
INHS
FS
INLS
CONF
OCLS
DLS
GLS
SR
CBOOT
4
5
6
7
8
9
Table 1. PIN DEFINITIONS
Descriptions of the pins listed in the table below can be found in the Functional Description section located on
page 12.
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16
Pin Name
CSNS
TEMP
EN
INHS
FS
INLS
CONF
OCLS
DLS
GLS
SR
CBOOT
GND
VPWR
OUT
Pin
Function
Reports
Reports
Input
Input
Reports
Input
Input
Input
Input
Output
Input
Input
Ground
Input
Output
Formal Name
Output Current Monitoring
Temperature Feedback
Enable
(Active High)
Serial Input High Side
Fault Status
(Active Low)
Serial Input Low Side
Configuration Input
Low Side Overload
Drain Low Side
Low Side Gate
Slew Rate Control
Bootstrap Capacitor
Ground
Positive Power Supply
Output
Definition
This pin is used to generate a ground-referenced voltage for the
microcontroller (MCU) to monitor output current.
This pin is used by the MCU to monitor board temperature.
This pin is used to place the device in a low-current Sleep Mode.
This input pin is used to control the output of the device.
This pin monitors fault conditions and is active LOW.
This pin is used to control an external low side N-channel MOSFET.
This input manages MOSFET N-channel cross-conduction.
This pin sets the V
DS
protection level of the external low side MOSFET.
This pin is the drain of the external low side N-channel MOSFET.
This output pin drives the gate of the external low side N-channel
MOSFET.
This pin controls the output slew rate.
This pin provides the high pulse current to drive the device.
This is the ground pin of the device.
This pin is the source input of operational power for the device.
These pins provide a protected high side power output to the load
connected to the device.
10
11
12
GND
13
VPWR
14
15
OUT
16
OUT
Figure 3. Pin Connections
2
3
1
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
ELECTRICAL RATINGS
Power Supply Voltage
Steady-state
Input/Output Pins Voltage
(1)
Symbol
Value
Unit
V
PWR
-16 to 41
INHS, INLS,
CONF, CSNS, FS,
TEMP, EN
V
OUT
41.0
-5.0
(2)
V
- 0.3 to 7.0
V
Output Voltage
Positive
Negative
Continuous Output Current
V
I
OUT
I
CL(CSNS)
I
CL(
EN)
V
SR
C
BOOT
V
OCLS
V
GLS
V
DLS
V
ESD
40.0
15.0
2.5
- 0.3 to 54.0
- 0.3 to 54.0
- 5.0 to 7.0
- 0.3 to 15.0
- 5.0 to 41.0
± 2000
± 750
± 500
A
mA
mA
V
V
V
V
V
V
CSNS Input Clamp Current
EN Input Clamp Current
SR Voltage
C
BOOT
Voltage
OCLS Voltage
Low Side Gate Voltage
Low Side Drain Voltage
ESD
Voltage
(3)
Human Body Model (HBM)
Charge Device Model (CDM)
Corner Pins (1, 12, 15, 16)
All Other Pins (2-11, 13-14)
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Storage Temperature
Thermal Resistance
(4)
°C
TA
TJ
- 40 to 125
- 40 to 150
- 55 to 150
1.0
30.0
Note 6
°C
T
STG
R
θ
JC
R
θ
JA
T
PPRT
°
C
°
C/W
Junction to Power Die Case
Junction to Ambient
Peak Package Reflow Temperature During Reflow
(5)
,
(6)
Notes
1. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN pins may cause a malfunction or permanent damage to the
device.
2. Continuous high side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
3. ESD testing is performed in accordance with the Human Body Model (HBM) (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω)
and the Charge Device
Model (CDM), Robotic (C
ZAP
= 4.0 pF).
4.
5.
6.
Device mounted on a 2s2p test board per JEDEC JESD51-2.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33981
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 6.0 V
≤
V
PWR
≤
27 V, -40°C
≤
T
A
≤
125°C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at T
A
= 25°C under nominal conditions, unless otherwise noted.
Characteristic
POWER INPUT (VPWR)
Battery Supply Voltage Range
Fully Operational
Extended
(7)
Symbol
Min
Typ
Max
Unit
V
PWR
6.0
4.5
I
PWR(ON)
–
I
PWR(SBY)
–
I
PWR(SLEEP)
–
–
V
PWR(UV)
V
PWR(UVHYS)
R
DS(ON)25
–
–
–
R
DS(ON)150
–
–
–
R
SD(ON)
–
I
OCH
75
C
SR
–
C
SR_ACC
1/20000
–
100
125
–
8.0
–
–
–
10.2
8.5
6.8
–
–
–
6.0
5.0
4.0
2.0
0.05
–
–
4.0
0.15
5.0
50.0
4.5
0.3
10.0
12.0
10.0
12.0
–
–
27.0
27.0
V
VPWR Supply Current
INHS = 1 and OUT Open
INLS = 0
VPWR Supply Current
INHS = INLS = 0, EN = 5.0 V, OUT Connected to GND
Sleep-state Supply Current
(V
PWR
< 14 V, EN
=
0 V, OUT Connected to GND)
T
A
= 25
°
C
T
A
= 125
°
C
Under-voltage Shutdown
Under-voltage Hysteresis
POWER OUTPUT (IOUT, VPWR)
Output Drain-to-Source ON Resistance
(
I
OUT
= 20 A, T
A
= 25
°
C)
V
PWR
= 6.0 V
V
PWR
= 9.0 V
V
PWR
= 13.0 V
Output Drain-to-Source ON Resistance (I
OUT
= 20 A, T
A
= 150
°
C)
V
PWR
= 6.0 V
V
PWR
= 9.0 V
V
PWR
= 13.0 V
Output Source-to-Drain ON Resistance
(
I
OUT
= -20 A, T
A
= 25
°
C)
(8)
V
PWR
= - 12 V
Output Overcurrent Detection Level
9.0 V < V
PWR
< 16 V
Current Sense Ratio
9.0 V < V
PWR
< 16 V, CSNS < 4.5 V
Current Sense Ratio (C
SR
) Accuracy
9.0 V < V
PWR
< 16 V, CSNS < 4.5 V
Output Current
5.0 A
15 A, 20 A and 30 A
Current Sense Voltage Clamp
I
CSNS
= 15 mA
mA
mA
μA
V
V
mΩ
mΩ
mΩ
A
–
%
-20
-15
V
CL(CSNS)
4.5
–
–
6.0
20
15
V
7.0
Notes
7. OUT can be commanded fully on, PWM is available at room. Low Side Gate driver is available. Protections and Diagnosis are not
available. Min/max parameters are not guaranteed.
8. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
PWR
.
33981
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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