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Datasheet> All Categories > storage> storage> IS27HC512-70W
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IS27HC512-70W

Description
OTP ROM, 64KX8, 70ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28
Categorystorage    storage   
File Size89KB，11 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
Download Datasheet Parametric Compare View All

IS27HC512-70W Overview

OTP ROM, 64KX8, 70ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28

IS27HC512-70W Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeDIP
package instruction0.600 INCH, PLASTIC, DIP-28
Contacts28
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PDIP-T28
JESD-609 codee0
length36.576 mm
memory density524288 bit
Memory IC TypeOTP ROM
memory width8
Number of functions1
Number of terminals28
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP28,.6
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height4.699 mm
Maximum standby current0.001 A
Maximum slew rate0.03 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm

IS27HC512-70W Preview

IS27HC512
IS27HC512
65,536 x 8 HIGH-SPEED CMOS EPROM
ISSI
NOVEMBER 1997
ISSI
®
®
FEATURES
• Fast access time: 45 ns
• Pin compatible with the IS27C512
• Low power consumption
— 50
µA
CMOS standby
• Industrial and commercial temperature ranges
available
• High-speed write programming
— Typically less than eight seconds
• 5
±10%
power supply tolerance available
• JEDEC-approved pinout
• Standard 28-pin DIP, and TSOP, and 32-pin
PLCC packages
DESCRIPTION
The
ISSI
IS27HC512 is an ultra-high-speed 512K-bit CMOS
Programmable Read-Only Memory. It utilizes the standard
JEDEC pinout making it functionally compatible with the
IS27C512, but with significantly fast access capability. This
superior random access capability results from a focused
high-speed design. This offers users bipolar speeds with
higher density, lower cost and proven reliability.
The device is ideal for use with the faster processors. This
IS27HC512 completely eliminates performance-draining wait
states without using bank-interleaving and caching tech-
niques. Designers may take full advantage of high-speed
digital signal processors and microprocessors by allowing
code to be executed at full speed directly out of EPROM.
Typical applications include laser printers, switching net-
works, graphics, workstations, high-speed modems, and digi-
tal signal processing.
The IS27HC512 uses
ISSI
'
s write programming algorithm
which allows the entire chip to be programmed in typically less
than thirty seconds.
This product is available in One-Time Programmable (OTP)
PDIP, PLCC, and TSOP packages over commercial and
industrial temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
DQ0-DQ7
8
OE/VPP
CE
OUTPUT ENABLE
CHIP ENABLE
AND
PROG LOGIC
OUTPUT
BUFFERS
Y
DECODER
A0-A15
Y
GATING
16
X
DECODER
524,288-BIT
CELL MATRIX
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
EP011-1F
11/13/97
1
IS27HC512
PIN CONFIGURATIONS
28-Pin DIP
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
A9
A11
OE (G)/VPP
A10
CE (E)
DQ7
DQ6
DQ5
DQ4
DQ3
ISSI
PIN DESCRIPTIONS
A0-A15
Address Inputs
Chip Enable Input
Data Inputs/Outputs
Output Enable Input/
Program Voltage Input
Power Supply Voltage
Ground
No Internal Connection
®
CE
(
E
)
DQ0-DQ7
OE
(
G
)/ V
PP
Vcc
GND
NC
32-Pin PLCC
28-Pin TSOP
VCC
A12
A15
A14
INDEX
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
5
6
7
8
9
10
11
12
13
A13
NC
A7
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE (G)/ VPP
A10
CE (E)
DQ7
DQ6
14
15
16
17
18
19
20
OE(G)/VPP
A11
A9
A8
A13
A14
VCC
A15
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
IS27HC512
Standard Pinout
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE (E)
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
GND
DQ1
DQ2
NC
DQ3
DQ4
DQ5
2
Integrated Silicon Solution, Inc.
EP011-1F
11/13/97
IS27HC512
FUNCTIONAL DESCRIPTION
Programming the IS27HC512
Upon delivery, the IS27HC512 has 524,288 bits in the
"ONE", or HIGH state. "ZEROs" are loaded into the
IS27HC512 through the procedure of programming.
The programming mode is entered when 12.5
±
0.25V is
applied to the
OE
/ V
PP
pin, V
CC
= 6V and
CE
is at V
IL
. For
programming, the data to be programmed is applied eight
bits in parallel to the data output pins.
The write programming algorithm reduces programming
time by using 100
µs
programming pulses followed by a
byte verification to determine whether the byte has been
successfully programmed. If the data does not verify, an
additional pulse is applied for a maximum of 25 pulses.
This process is repeated while sequencing through each
address of the EPROM.
The write programming algorithm programs and verifies at
V
CC
= 6V and
OE
/ V
PP
= 12.5V. After the final address is
completed, all byte are compared to the original data with
V
CC
= 5.25V.
Program Inhibit
Programming of multiple IS27HC512s in parallel with
different data is also easily accomplished. Except for
CE
,
all like inputs of the parallel IS27HC512 may be common.
A TTL low-level program pulse applied to an IS27HC512
CE
input with
OE
/ V
PP
= 12.5
±
0.25V will program that
IS27HC512. A high-level
CE
input inhibits the other
IS27HC512 from being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with
CE
at V
IL
and
OE
/ V
PP
at
V
IL
.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and type. This mode is intended for use by programming
equipment for the purpose of automatically matching the
device to be programmed with its corresponding program-
ming algorithm. This mode is functional in the 25°C
±
5°C
ambient temperature range that is required when pro-
gramming the IS27HC512.
ISSI
®
To activate this mode, the programming equipment must
force 12.0
±
0.5V on address line A9 of the IS27HC512.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from V
IL
to V
IH
.
All other address lines must be held at V
IL
during auto
select mode.
Byte 0 (A0 = V
IL
) represents the manufacturer code, and
byte 1 (A0 = V
IH
), the device identifier code. For the
IS27HC512, these two identifier bytes are given in the
Mode Select table. All identifiers manufacturer and device
codes will possess odd parity, with the MSB (DQ7) defined
as the parity bit.
Read Mode
The IS27HC512 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (
CE
) is the power control and should
be used for device selection. Assuming that addresses are
stable, address access time (t
ACC
) is equal to the delay
from
CE
to output (t
CE
). Output Enable (
OE
) is the output
control and should be used to get data to the output pins,
independent of device selection. Data is available at the
outputs t
OE
after the falling edge of
OE
assuming that
CE
has been LOW and addresses have been stable for at
least t
ACC
– t
OE
.
Standby Mode
The IS27HC512 has a standby mode which reduces the
maximum V
CC
active current. It is placed in standby mode
when
CE
is at V
IH
. The amount of current drawn in standby
mode depends on the frequency and the number of
address pins switching. The IS27HC512 is specified with
50% of the address lines toggling at 5 MHz. A reduction of
the frequency or quantity of address lines toggling will
significantly reduce the actual standby current.
Integrated Silicon Solution, Inc.
EP011-1F
11/13/97
3
IS27HC512
Output OR-Tieing
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation, and
2. Assurance that output bus contention will not
occur.
It is recommended that
CE
be decoded and used as the
primary device-selecting function, while
OE
/ V
PP
be made
a common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins are
only active when data is desired from a particular memory
device.
ISSI
®
System Applications
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output capaci-
tance loading of the device at a minimum, a 0.1
µF
ceramic
capacitor (high-frequency, low inherent inductance) should
be used on each device between V
CC
and GND to mini-
mize transient effects. In addition, to overcome the voltage
drop caused by the inductive effects of the printed circuit
board traces on EPROM arrays, a 4.7
µF
bulk electrolytic
capacitor should be used between V
CC
and GND for each
eight devices. The location of the capacitor should be
close to where the power supply is connected to the array.
TRUTH TABLE
(1,2,4)
Mode
Read
Output Disable
Standby
Program
Program Verify
Program Inhibit
Auto Select
(3,5)
Manufacturer Code
Device Code
CE
V
IL
X
V
IH
V
IL
V
IL
V
IH
V
IL
V
IL
OE
/ V
PP
V
IL
V
IH
X
V
PP
V
IL
V
PP
V
IL
V
IL
A0
X
X
X
X
X
X
V
IL
V
IH
A9
X
X
X
X
X
X
V
H
V
H
Outputs
D
OUT
Hi-Z
Hi-Z
D
IN
D
OUT
Hi-Z
D5H
91H
Notes:
1. V
H
= 12.0V
±
0.5V.
2. X = Either V
IH
or V
IL
.
3. A1-A8 = A10-A15 = V
IL
.
4. See DC Programming Characteristics for V
PP
voltage during programming.
5. The IS27HC512 can use the same write algorithm during program as other IS27C512 or IS27512 devices.
LOGIC SYMBOL
16
A0-A15
8
DQ0-DQ7
CE (E)
OE (G)/V
PP
4
Integrated Silicon Solution, Inc.
EP011-1F
11/13/97
IS27HC512
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Parameter
Terminal Voltage with Respect to GND
All pins except A9 and V
PP
V
PP
A9
V
CC
Ambient Temperature with Power Applied
Storage Temperature (OTP)
Storage Temperature (All others)
Value
–0.6 to V
CC
+ 0.5
(2)
V
CC
– 0.3 to 13.5
(2,3)
–0.6 to 13.5
(2,3)
–0.6 to 7.0
(2)
–65 to +125
–65 to +125
–65 to +150
Unit
V
V
V
V
°C
°C
°C
ISSI
®
T
A
T
STG
T
STG
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods less than 10
ns. Maximum DC voltage on output pins is Vcc + 0.5V which may overshoot to Vcc + 2.0V for periods less than
10 ns.
3. Maximum DC voltage on A9 or V
PP
may overshoot to +13.5V for periods less than 10 ns.
OPERATING RANGE
Range
Commercial
Industrial
(1)
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V
±
10%
5V
±
10%
Note:
1. Operating ranges define those limits between which the
functionally of the device is guaranteed.
DC ELECTRICAL CHARACTERISTICS
(1,2,3)
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(4)
Input LOW Voltage
(4)
Input Load Current
Output Leakage Current
V
IN
= 0V to +V
CC
V
OUT
= 0V to +V
CC
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.0
–0.3
—
—
Max.
—
0.45
V
CC
+ 0.5
0.8
5.0
10
Unit
V
V
V
V
µA
µA
Notes:
1. V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. Never try to force V
PP
LOW to 1V
below V
CC
. Manufacturer suggests to tie V
PP
and V
CC
together during the READ operation.
2.
Caution:
the IS27HC512 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied.
3. Minimum DC input voltage is –0.5V. During transitions, the inputs may undershoot to –2.0V for periods less than 10 ns.
Maximum DC voltage on output pins is V
CC
+ 0.5V which may overshoot to V
CC
+ 2.0V for periods less than 10 ns.
4. Tested under static DC conditions.
Integrated Silicon Solution, Inc.
EP011-1F
11/13/97
5
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Description OTP ROM, 64KX8, 70ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 OTP ROM, 64KX8, 45ns, CMOS, PQCC32, PLASTIC, LCC-32 OTP ROM, 64KX8, 45ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 OTP ROM, 64KX8, 55ns, CMOS, PDSO28, TSOP-28 OTP ROM, 64KX8, 55ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 OTP ROM, 64KX8, 70ns, CMOS, PQCC32, PLASTIC, LCC-32 OTP ROM, 64KX8, 70ns, CMOS, PQCC32, PLASTIC, LCC-32
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
Parts packaging code DIP QFJ DIP TSOP DIP QFJ QFJ
package instruction 0.600 INCH, PLASTIC, DIP-28 PLASTIC, LCC-32 0.600 INCH, PLASTIC, DIP-28 TSOP-28 0.600 INCH, PLASTIC, DIP-28 PLASTIC, LCC-32 PLASTIC, LCC-32
Contacts 28 32 28 28 28 32 32
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
Maximum access time 70 ns 45 ns 45 ns 55 ns 55 ns 70 ns 70 ns
I/O type COMMON COMMON COMMON COMMON COMMON COMMON COMMON
JESD-30 code R-PDIP-T28 R-PQCC-J32 R-PDIP-T28 R-PDSO-G28 R-PDIP-T28 R-PQCC-J32 R-PQCC-J32
JESD-609 code e0 e0 e0 e0 e0 e0 e0
length 36.576 mm 13.97 mm 36.576 mm 11.8 mm 36.576 mm 13.97 mm 13.97 mm
memory density 524288 bit 524288 bit 524288 bit 524288 bit 524288 bit 524288 bit 524288 bit
Memory IC Type OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM OTP ROM
memory width 8 8 8 8 8 8 8
Number of functions 1 1 1 1 1 1 1
Number of terminals 28 32 28 28 28 32 32
word count 65536 words 65536 words 65536 words 65536 words 65536 words 65536 words 65536 words
character code 64000 64000 64000 64000 64000 64000 64000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 85 °C
organize 64KX8 64KX8 64KX8 64KX8 64KX8 64KX8 64KX8
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP QCCJ DIP TSOP1 DIP QCCJ QCCJ
Encapsulate equivalent code DIP28,.6 LDCC32,.5X.6 DIP28,.6 TSSOP28,.53,22 DIP28,.6 LDCC32,.5X.6 LDCC32,.5X.6
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE CHIP CARRIER IN-LINE SMALL OUTLINE, THIN PROFILE IN-LINE CHIP CARRIER CHIP CARRIER
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
power supply 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 4.699 mm 3.55 mm 4.699 mm 1.2 mm 4.699 mm 3.55 mm 3.55 mm
Maximum standby current 0.001 A 0.001 A 0.001 A 0.001 A 0.001 A 0.001 A 0.001 A
Maximum slew rate 0.03 mA 0.03 mA 0.03 mA 0.03 mA 0.03 mA 0.03 mA 0.03 mA
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount NO YES NO YES NO YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE J BEND THROUGH-HOLE GULL WING THROUGH-HOLE J BEND J BEND
Terminal pitch 2.54 mm 1.27 mm 2.54 mm 0.55 mm 2.54 mm 1.27 mm 1.27 mm
Terminal location DUAL QUAD DUAL DUAL DUAL QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 15.24 mm 11.43 mm 15.24 mm 8 mm 15.24 mm 11.43 mm 11.43 mm

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