HY57V561620FLT-H datasheet, PDF

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HY57V561620FLT-H: DescriptionSynchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size684KB，48 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V561620FLT-H Overview

Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

HY57V561620FLT-H Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
length	22.22 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.17 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

256M (16Mx16bit) Hynix SDRAM

Memory

Memory Cell Array

- Organized as 4banks of 4,194,304 x 16

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.3 / Dec. 2009

111

Synchronous DRAM Memory 256Mbit

HY57V561620F(L)T(P) Series

DESCRIPTION

The Hynix Synchronous DRAM is suited for advaced-consumer application which use the batteries such as Image dis-

player application (Digital still camera etc.) and portable applications (portable multimedia player and portable audio

player). Also, Hynix SDRAMs is used high-speed consumer applications. Short for Hynix Synchronous DRAM, a type of

DRAM that can run at much higher clock speeds memory.

The Hynix HY57V561620F(L)T(P) Synchronous DRAM is 268,435,456bit CMOS Synchronous DRAM, ideally suited for

the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks

of 4,194,304 x 16 I/O.

Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous

DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization

with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16

Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.

The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4,

8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is

initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve

high-speed operation. This architecture is compartible with the 2n rule of prefetch architectures, but it also allows the

column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one

bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed,

randon-access operation.

Read and write accesses to the Hynix Synchronous DRAM are burst oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command.

The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be

accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and

the starting column location for the burst access.

All inputs are LVTTL compatible. Devices will have a V

and V

DDQ

supply of 3.3V (nominal).

Rev 1.3 / Dec. 2009

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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