PRELIMINARY
PSoC
®
5: CY8C53 Family Datasheet
Programmable System-on-Chip (PSoC
®
)
General Description
With its unique array of configurable blocks, PSoC
®
5 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C53 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C53 family can handle dozens of data acquisition channels and analog inputs on
every GPIO pin. The CY8C53 family is also a high-performance configurable digital system with some part numbers including
interfaces such as USB, multi-master I
2
C, and controller area network (CAN). In addition to communication interfaces, the CY8C53
family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM
®
Cortex™-M3
microprocessor core. Designers can easily create system-level designs using a rich library of prebuilt components and boolean
primitives using PSoC
®
Creator™, a hierarchical schematic design entry tool. The CY8C53 family provides unparalleled opportunities
for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware
updates.
Features
32-bit ARM Cortex-M3 CPU core
DC to 80 MHz operation
Flash program memory, up to 256 KB, 100,000 write cycles,
20-year retention, multiple security features
Up to 64 KB SRAM memory
2-KB electrically erasable programmable read-only memory
(EEPROM) memory, 1 million cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AMBA high-performance bus (AHB) bus access
• Programmable chained descriptors and priorities
• High bandwidth 32-bit transfer support
Low voltage, ultra low power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5 V input to 1.8 V to
5.0 V output
2 mA at 6 MHz
Low power modes including:
• 2-µA sleep mode with real time clock (RTC) and
low-voltage detect (LVD) interrupt
• 300-nA hibernate mode with RAM retention
Versatile I/O system
[1]
28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs )
Any GPIO to any digital or analog peripheral routability
LCD direct drive from any GPIO, up to 46x16 segments
®
[2]
CapSense support from any GPIO
1.2 V to 5.5 V I/O interface voltages, up to 4 domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIOs configurable as open drain high/low,
pull-up/pull-down, High-Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
20 to 24 programmable
logic device (PLD)
based universal
digital blocks (UDBs)
[1]
Full CAN 2.0b 16 RX, 8 TX buffers
[1]
Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator
Up to four 16-bit configurable timer, counter, and PWM blocks
Library of standard peripherals
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• SPI, UART, and I
2
C
• Many others available in catalog
Library of advanced peripherals
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generator
• Local interconnect network (LIN) bus 2.0
• Quadrature decoder
Analog peripherals (1.71 V
V
DDA
5.5 V)
1.024 V ± 0.1% internal voltage reference across –40 °C to
+85 °C (14 ppm/°C)
Successive approximation register (SAR)
analog-to-digital
converter (ADC), 12-bit at 1 Msps
Two 8-bit 8 Msps current digital-to-analog converters (DAC)
(IDACs) or 1 Msps voltage DACs (VDACs)
Four comparators with 95-ns response time
Two uncommitted opamps with 25-mA drive capability
Two configurable multifunction analog blocks. Example
configurations are programmable gain amplifier (PGA),
transimpedance amplifier (TIA), mixer, and sample and hold
CapSense support
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), single-wire
viewer (SWV), and TRACEPORT interfaces
Cortex-M3 flash patch and breakpoint (FPB) block
Cortex-M3 Embedded Trace Macrocell™ (ETM™)
generates an instruction trace stream.
Cortex-M3 data watchpoint and trace (DWT) generates data
trace information
Cortex-M3 instrumentation trace macrocell (ITM) can be
used for printf-style debugging
DWT, ETM, and ITM blocks communicate with off-chip debug
and trace systems via the SWV or TRACEPORT
2
Bootloader programming supportable through I C, SPI,
UART, USB, and other interfaces
Precision, programmable clocking
3- to 74-MHz internal oscillator over full temperature and
voltage range
4- to 33-MHz crystal oscillator for crystal PPM accuracy
Internal PLL clock generation up to 80 MHz
32.768-kHz watch crystal oscillator
Low power internal oscillator at 1, 33, and 100 kHz
Temperature and packaging
–40°C to +85°C degrees industrial temperature
48-pin SSOP, 68-pin QFN, and 100-pin TQFP package
options
Notes
1. This feature on select devices only. See
Ordering Information
on page 91 for details.
2. GPIOs with opamp outputs are not recommended for use with CapSense
Cypress Semiconductor Corporation
Document Number: 001-55035 Rev. *G
•
198 Champion Court
•
San Jose CA 95134-1709
,
•
408-943-2600
Revised September 2, 2010
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PRELIMINARY
PSoC
®
5: CY8C53 Family Datasheet
Contents
1. Architectural Overview ................................................ 3
2. Pinouts .......................................................................... 5
3. Pin Descriptions ........................................................... 9
4. CPU .............................................................................. 10
4.1 ARM Cortex-M3 CPU .......................................... 10
4.2 Cache Controller ................................................. 12
4.3 DMA and PHUB .................................................. 12
4.4 Interrupt Controller .............................................. 14
5. Memory ........................................................................ 16
5.1 Static RAM .......................................................... 16
5.2 Flash Program Memory ....................................... 16
5.3 Flash Security ...................................................... 16
5.4 EEPROM ............................................................. 16
5.5 External Memory Interface .................................. 16
5.6 Memory Map ....................................................... 18
6. System Integration ..................................................... 19
6.1 Clocking System .................................................. 19
6.2 Power System ..................................................... 23
6.3 Reset ................................................................... 26
6.4 I/O System and Routing ...................................... 28
7. Digital Subsystem ...................................................... 34
7.1 Example Peripherals ........................................... 34
7.2 Universal Digital Block ......................................... 38
7.3 UDB Array Description ........................................ 41
7.4 DSI Routing Interface Description ....................... 42
7.5 CAN ..................................................................... 43
7.6 USB ..................................................................... 45
7.7 Timers, Counters, and PWMs ............................. 46
7.8 I
2
C ....................................................................... 46
8. Analog Subsystem ..................................................... 47
8.1 Analog Routing .................................................... 48
8.2 Successive Approximation ADC .......................... 50
8.3 Comparators ........................................................ 50
8.4 Opamps ............................................................... 52
8.5 Programmable SC/CT Blocks ............................. 52
8.6 LCD Direct Drive ................................................. 53
8.7 CapSense ............................................................ 54
8.8 Temp Sensor ....................................................... 54
8.9 DAC ..................................................................... 54
8.10 Up/Down Mixer .................................................. 55
8.11 Sample and Hold ............................................... 56
9. Programming, Debug Interfaces, Resources ........... 56
9.1 JTAG Interface .................................................... 57
9.2 SWD Interface ..................................................... 57
9.3 Debug Features ................................................... 57
9.4 Trace Features .................................................... 57
9.5 SWV and TRACEPORT Interfaces ..................... 57
9.6 Programming Features ........................................ 57
9.7 Device Security ................................................... 57
10. Development Support .............................................. 58
10.1 Documentation .................................................. 58
10.2 Online ................................................................ 58
10.3 Tools .................................................................. 58
11. Electrical Specifications .......................................... 59
11.1 Absolute Maximum Ratings ............................... 59
11.2 Device Level Specifications ............................... 60
11.3 Power Regulators .............................................. 62
11.4 Inputs and Outputs ............................................ 63
11.5 Analog Peripherals ............................................ 69
11.6 Digital Peripherals ............................................. 78
11.7 Memory ............................................................. 81
11.8 PSoC System Resources .................................. 86
11.9 Clocking ............................................................. 88
12. Ordering Information ................................................ 91
12.1 Part Numbering Conventions ............................ 93
13. Packaging .................................................................. 94
14. Acronyms .................................................................. 96
15. Reference Documents .............................................. 97
16. Document Conventions ........................................... 98
16.1 Units of Measure ............................................... 98
17. Revision History ....................................................... 99
18. Sales, Solutions, and Legal Information .............. 102
Document Number: 001-55035 Rev. *G
Page 2 of 102
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PRELIMINARY
PSoC
®
5: CY8C53 Family Datasheet
1. Architectural Overview
Introducing the CY8C53 family of ultra low-power, flash Programmable System-on-Chip (PSoC
®
) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C53 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
GPIOs
Usage Example for UDB
Sequencer
4 to 33 MHz
( Optional
)
System Wide
Resources
Xtal
Osc
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit
Timer
UDB
Quadrature Decoder
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
CAN
2.0
I2C
Master
/
Slave
SIO
22
UDB
UDB
Clock Tree
UDB
I 2C Slave
UDB
UDB
8- Bit SPI
UDB
12- Bit SPI
UDB
8- Bit
Timer
Logic
UDB
GPIOs
UDB
UDB
UDB
UDB
IMO
4x
Timer
Counter
PWM
FS USB
2.0
USB
PHY
32.768 KHz
( Optional
)
Logic
UDB
UART
UDB
UDB
12- Bit PWM
UDB
UDB
UDB
RTC
Timer
System Bus
WDT
and
Wake
GPIOs
Memory System
EEPROM
SRAM
CPU System
8051 or
Cortex M3 CPU
Interrupt
Controller
Program &
Debug
Program
Debug &
Trace
EMIF
ILO
Clocking System
Power Management
System
FLASH
Cache
Controller
PHUB
DMA
Boundary
Scan
Analog System
LCD Direct
Drive
SIOs
POR and
LVD
Sleep
Power
1.71 to
5.5 V
1.8 V LDO
SMP
2 x SC/ CT Blocks
(TIA, PGA, Mixer etc
)
Temperature
Sensor
CapSense
ADC
SAR
ADC
+
2x
Opamp
-
3 per
Opamp
2 x DAC
4x
CMP
-
0. 5 to 5.5V
( Optional
)
Document Number: 001-55035 Rev. *G
GPIOs
+
GPIOs
GPIOs
GPIOs
Page 3 of 102
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PRELIMINARY
PSoC
®
5: CY8C53 Family Datasheet
Figure 1-1
illustrates the major components of the CY8C53
family. They are:
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C53 family also offers a SAR ADC. Featuring 12-bit
conversions at up to 1 M samples per second, it also offers low
nonlinearity and offset errors and SNR better than 70 dB. It is
well suited for a variety of higher speed analog applications.
Two high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADC and DACs, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of pre-built
and tested standard digital peripherals (UART, SPI, LIN, PRS,
CRC, timer, counter, PWM, AND, OR, and so on) that are
mapped to the UDB array. The designer can also easily create a
digital circuit using boolean primitives by means of graphical
design entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C53 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I
2
C slave, master, and multimaster;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the
“Example
Peripherals”
section on page 34 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 34 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1% error
over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Analog mixers
Voltage references
Analog-to-Digital Converters (ADC)
Digital-to-Analog Converters (DACs)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the
“Analog Subsystem”
section on page 47 of this
datasheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 80 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. The designer can enable
an error correcting code (ECC) for high reliability applications. A
powerful and flexible protection model secures the user's
sensitive information, allowing selective memory block locking
for read and write protection. Two KB of byte-writable EEPROM
is available on-chip to store application data. Additionally,
selected configuration options such as boot speed and pin drive
mode are stored in nonvolatile memory. This allows settings to
activate immediately after POR.
Document Number: 001-55035 Rev. *G
Page 4 of 102
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PRELIMINARY
PSoC
®
5: CY8C53 Family Datasheet
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
DDIO
pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow V
OH
to be set independently of V
DDIO
when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I
2
C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with Full-Speed USB the USB physical interface is
also provided (USBIO). When not using USB these pins may
also be used for limited digital functionality and device
programming. All the features of the PSoC I/Os are covered in
detail in the
“I/O System and Routing”
section on page 28 of this
datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 74 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 80 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power internal low speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in real time clock (RTC) applications. The
clocks, together with programmable clock dividers, provide the
flexibility to integrate most timing requirements.
The CY8C53 family supports a wide supply operating range from
1.71 to 5.5 V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 0.5 V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a
3.3 V supply for LCD glass drive. The boost’s output is available
on the V
BOOST
pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 300-nA hibernate mode with RAM retention and a 2-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the
“Power
System”
section on page 23 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. Using these standard interfaces
enables the designer to debug or program the PSoC with a
variety of hardware solutions from Cypress or third party
vendors. The Cortex-M3 debug and trace modules include FPB,
DWT, ETM, and ITM. These modules have many features to help
solve difficult debug and trace problems. Details of the
programming, test, and debugging interfaces are discussed in
the
“Programming, Debug Interfaces, Resources”
section on
page 56 of this datasheet.
2. Pinouts
The V
DDIO
pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in
Figure 2-2
and
Figure 2-3.
Using the V
DDIO
pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each V
DDIO
may sink up to 100 mA total to its
associated I/O pins and opamps. On the 68-pin and 100-pin
devices each set of V
DDIO
associated pins may sink up to
100 mA. The 48 pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
Document Number: 001-55035 Rev. *G
Page 5 of 102
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