LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
DESCRIPTION
The
LPR520
and
LPR521
are functionally
compatible with the IDT29FCT520/
IDT29FCT521 and AMD Am29520/
Am29521 but have 16-bit inputs and
outputs. They are implemented in low
power CMOS.
The LPR520 and LPR521 contain four
registers which can be configured as
two independent, 2-level pipelines or
as one 4-level pipeline.
The Instruction pins, I
1-0
, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the LPR520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
LPR521 differs from the LPR520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I
1-0
may be set to prevent any register
from changing.
The S
1-0
select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
FEATURES
u
Four 16-bit Registers
u
Implements Double 2-Stage Pipe-
line or Single 4-Stage Pipeline
Register
u
Hold, Shift, and Load Instructions
u
Separate Data In and Data Out Pins
u
High-Speed, Low Power CMOS
Technology
u
Three-State Outputs
u
DESC SMD No. 5962-89716
u
Available 100% Screened to
MIL-STD-883, Class B
u
Package Styles Available:
• 40-pin Plastic DIP
• 40-pin Ceramic DIP
• 44-pin Plastic LCC, J-Lead
• 44-pin Ceramic LCC
T
ABLE
1.
LPR520 I
NSTRUCTION
T
ABLE
I
1
L
L
H
H
I
0
L
H
L
H
Description
D©R1
HOLD
D©R1
R1©R2
HOLD
R1©R2
R2©R3
D©R3
HOLD
R3©R4
R3©R4
HOLD
ALL REGISTERS ON HOLD
T
ABLE
2.
LPR521 I
NSTRUCTION
T
ABLE
I
1
L
L
H
H
I
0
L
H
L
H
Description
D©R1
HOLD
D©R1
R1©R2
HOLD
HOLD
R2©R3
D©R3
HOLD
R3©R4
HOLD
HOLD
LPR520/521 B
LOCK
D
IAGRAM
ALL REGISTERS ON HOLD
T
ABLE
3.
REGISTER 1
REGISTER 2
O
UTPUT
S
ELECT
S
1
S
0
MUX
Register Selected
Register 4
Register 3
Register 2
Register 1
16
D
15-0
L
L
REG 1
REG 2
REG 3
REG 4
L
H
L
H
H
MUX
16
Y
15-0
OE
2
H
REGISTER 3
REGISTER 4
S
1-0
2
I
1-0
CLK
Pipeline Registers
1
06/30/95–LDS.P520/1-K
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature .......................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground .......................................................................... –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–55°C to +125°C
Supply
Voltage
4.75 V
≤
V
CC
≤
5.25 V
4.50 V
≤
V
CC
≤
5.50 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
(Note 3)
Test Condition
V
CC
= Min.,
I
OH
= –2.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
Min
2.4
Typ
Max
Unit
V
0.5
2.0
0.0
V
CC
0.8
±20
±20
10
40
1.0
V
V
V
µA
µA
mA
mA
Ground
≤
V
IN
≤
V
CC
(Note 12)
Ground
≤
V
OUT
≤
V
CC
(Note 12)
(Notes 5, 6)
(Note 7)
Pipeline Registers
2
06/30/95–LDS.P520/1-K
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
ENA
/t
DIS
test), and input levels of
nominally 0 to 3.0 V. Output loading
may be a resistive divider which
provides for specified
I
OH
and
I
OL
at an
output voltage of
V
OH
min and
V
OL
2. The products described by this spec- max respectively. Alternatively, a
ification include internal circuitry de- diode bridge with upper and lower
signed to protect the chip from damag- current sources of
I
OH
and
I
O L
ing substrate injection currents and ac- respectively, and a balancing voltage of
cumulations of static charge. Never- 1.5 V may be used.
Parasitic
theless, conventional precautions capacitance is 30 pF minimum, and
should be observed during storage, may be distributed. For
t
ENABLE
and
handling, and use of these circuits in
t
DISABLE
measurements, the load
order to avoid exposure to excessive current is increased to 10 mA to reduce
electrical stress values.
the RC delay component of the
3. This device provides hard clamping measurement.
of transient undershoot and overshoot. This device has high-speed outputs ca-
Input levels below ground or above
V
CC
pable of large instantaneous current
will be clamped beginning at –0.6 V and pulses and fast turn-on/turn-off times.
V
CC
+ 0.6 V. The device can withstand As a result, care must be exercised in
indefinite operation with inputs in the the testing of this device. The following
range of –0.5 V to +7.0 V. Device opera- measures are recommended:
tion will not be adversely affected, how-
ever, input current levels will be well in a. A 0.1 µF ceramic capacitor should be
excess of 100 mA.
installed between
V
CC
and Ground
leads as close to the Device Under Test
4. Actual test conditions may vary (DUT) as possible. Similar capacitors
from those designated but operation is should be installed between device
V
CC
guaranteed as specified.
and the tester common, and device
5. Supply current for a given applica- ground and tester common.
tion can be accurately approximated b. Ground and
V
CC
supply planes
by:
must be brought directly to the DUT
NCV
2
F
socket or contactor fingers.
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values be-
yond those indicated in the Operating
Conditions table is not implied. Expo-
sure to maximum rating conditions for
extended periods may affect reliability.
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. Transition is measured ±200 mV
from steady-state voltage with speci-
fied loading.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
F
IGURE
1.
t
DIS
OE
T
HRESHOLD
L
EVELS
t
ENA
0.2 V
0.2 V
HIGH IMPEDANCE
TRISTATE
OUTPUTS
0.2 V
0.2 V
4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
c. Input voltages should be adjusted to
compensate for inductive ground and
V
CC
noise to maintain required DUT
input levels relative to the DUT ground
pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
Pipeline Registers
4
06/30/95–LDS.P520/1-K
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