HY62256AR1-70 datasheet, PDF - EEWORLD Datasheet

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HY62256AR1-70: DescriptionStandard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, REVERSE, TSOP1-28; Categorystorage storage; File Size816KB，14 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY62256AR1-70 Overview

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, REVERSE, TSOP1-28

HY62256AR1-70 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	TSOP
package instruction	TSOP1-R, TSSOP28,.53,22
Contacts	28
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	70 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G28
JESD-609 code	e0
length	11.8 mm
memory density	262144 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	28
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX8
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1-R
Encapsulate equivalent code	TSSOP28,.53,22
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
reverse pinout	YES
Maximum seat height	1.2 mm
Maximum standby current	0.001 A
Minimum standby current	2 V
Maximum slew rate	0.07 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.55 mm
Terminal location	DUAL
width	8 mm

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Data Sheet-sram/62256ald1

http://www.hea.com/hean2/sram/62256ald1.htm

HY62256A-(I) Series

32Kx8bit CMOS SRAM

Description

Features

The

Fully static operation and

HY62256A/HY62256A-I

Tri-state outputs

is a high-speed, low

TTL compatible inputs

power and 32,786 x 8-bits

and outputs

CMOS Static Random

Low power consumption

Access Memory

-2.0V(min.) data

fabricated using

retention

Hyundai's high

Standard pin

performance CMOS

configuration

process technology. The

-28 pin 600 mil PDIP

HY62256A/HY62256A-I

-28 pin 330 mil SOP

has a data retention mode

-28 pin 8x13.4 mm

that guarantees data to

TSOP-1

remain valid at the

(standard and reversed)

minimum power supply

voltage of 2.0 volt. Using

the CMOS technology,

supply voltages from 2.0

to 5.5 volt has little effect

on supply current in the

data retention mode. The

HY62256A/HY62256A-I

is suitable for use in low

voltage operation and

battery back-up

application.

1 of 2

22/10/97 12:30

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