8-Mbit (512K x 16) MoBL Static RAM
Features
■
CY62157DV30 MoBL
®
Temperature ranges
❐
Industrial: –40 °C to 85 °C
Very high speed: 55 ns
Wide voltage range: 2.20 V–3.60 V
Pin-compatible with CY62157CV25, CY62157CV30, and
CY62157CV33
Ultra-low active power
❐
Typical active current: 1.5 mA @ f = 1 MHz
❐
Typical active current: 12 mA @ f = f
max
Ultra-low standby power
Easy memory expansion with CE
1
, CE
2
, and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
Available in Pb-free and non Pb-free 48-ball fine ball grid
array (FBGA), and Pb-free 44-pin thin small outline package
(TSOPII) package
■
■
■
■
This is ideal for providing More Battery Life (MoBL
®
) in
portable applications such as cellular telephones.The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can also be put into
standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE and BLE are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed in a high-impedance state when:
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the
address pins (A
0
through A
18
). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O
8
through I/O
15
) is written into
the location specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
0
to I/O
7
. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O
8
to I/O
15
. See the truth table for a complete description
of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines.
■
■
■
■
■
Functional Description
The CY62157DV30 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
DATA-IN DRIVERS
512K × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
CE
2
CE
1
Power-down
Circuit
Cypress Semiconductor Corporation
Document #: 38-05392 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 25, 2010
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CY62157DV30 MoBL
®
Contents
Product Portfolio .............................................................. 3
Pin Configuration .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics
....................................... 5
Data Retention Waveform................................................. 5
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definition ........................................... 11
Package Diagram ............................................................ 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Document #: 38-05392 Rev. *J
Page 2 of 15
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CY62157DV30 MoBL
®
Product Portfolio
Power Dissipation
Product
Range
V
CC
Range (V)
Min
CY62157DV30LL Industrial
2.2
Typ
[1]
3.0
Max
3.6
55, 70
Speed
(ns)
Operating I
CC
, (mA)
f = 1MHz
Typ
[1]
1.5
Max
3
f = f
max
Typ
[1]
12
Max
15
Standby I
SB2
,
(A)
Typ
[1]
2
Max
8
Pin Configuration
[2, 3, 4]
1
BLE
I/O
8
I/O
9
V
SS
V
CC
2
OE
BHE
I/O
10
I/O
11
3
A
0
A
3
A
5
A
17
4
48-Ball FBGA Pinout
Top View
5
A
2
CE
1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE
2
I/O
0
I/O
2
Vcc
Vss
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
44-pin TSOP II Pinout
Top View
A
4
A
3
A
2
A
1
A
0
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
V
SS
I/O
4
I/O
5
I/O
6
I/O
7
WE
A
18
A
17
A
16
A
15
A
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
I/O
12
DNU
A
14
A
12
A
9
I/O
14
I/O
13
I/O
15
A
18
NC
A
8
A
5
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
A
8
A
9
A
10
A
11
A
12
A
13
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25 °C.
2. NC pins are not internally connected on the die.
3. DNU pins have to be left floating.
4. The 44-TSOPII package device has only one chip enable pin (CE).
Document #: 38-05392 Rev. *J
Page 3 of 15
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CY62157DV30 MoBL
®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied .......................................... –55 °C to + 125 °C
Supply voltage to ground
potential .......................................... –0.3 V to V
CC(max)
+ 0.3 V
DC voltage applied to outputs
in High-Z State
[5, 6]
......................... –0.3 V to V
CC(max)
+ 0.3 V
DC input voltage
[5, 6]
....................... –0.3 V to V
CC(max)
+ 0.3 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... >2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ...................................................... >200 mA
Operating Range
Device
CY62157DV30LL
Range
Industrial
Ambient
Temperature
(T
A
)
–40 °C to +85 °C
V
CC
[
7]
2.20 V to
3.60 V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
I
OH
= –0.1 mA
I
OH
= –1.0 mA
I
OL
= 0.1 mA
I
OL
= 2.1 mA
V
CC
= 2.2 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 2.7 V to 3.6 V
Input leakage
current
Output leakage
current
V
CC
Operating
supply current
Automatic
Power-down
current — CMOS
inputs
Automatic
Power-down
current -CMOS
inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
CE
1
> V
CC
0.2
V or CE
2
< 0.2 V or
(BHE and BLE) > V
CC
0.2
V,
V
IN
> V
CC
– 0.2 V, V
IN
< 0.2 V
f = f
MAX
(Address and Data Only),
f = 0 (OE, WE), V
CC
= 3.60V
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V,
(BHE and BLE) > V
CC
0.2
V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= 3.60 V
Ind’l
Ind’l
V
CC
= V
CCmax
LL
I
OUT
= 0 mA LL
CMOS levels
Ind’l
LL
Test Conditions
V
CC
= 2.20 V
V
CC
= 2.70 V
V
CC
= 2.20 V
V
CC
= 2.70 V
-55
Min
2.0
2.4
–
–
1.8
2.2
–0.3
–0.3
–1
–1
–
Typ
[8]
–
–
–
–
–
–
–
–
–
–
12
1.5
–
2
Max
–
–
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
+1
15
3
8
Unit
V
V
V
V
V
V
V
V
A
A
mA
mA
A
Input LOW voltage V
CC
= 2.2 V to 2.7 V
I
SB2
Ind’l
LL
–
2
8
A
Capacitance
Parameter
[9, 10]
C
IN
C
OUT
Description
Input capacitance
Output capacitance
Test Conditions
T
A
= 25 °C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Notes
5. V
IL(min.)
= –2.0 V for pulse durations less than 20 ns.
6. V
IH(max)
= V
CC
+0.75 V for pulse duration less than 20 ns.
7. Full device AC operation assumes a 100
s
ramp time from 0 to V
CC
(min) and 200
s
wait time after V
CC
stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
9. Tested initially and after any design or process changes that may affect these parameters.
10. The input capacitance on the CE
2
pin of the FBGA package and on the BHE pin of the 44TSOPII package is 15 pF.
Document #: 38-05392 Rev. *J
Page 4 of 15
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CY62157DV30 MoBL
®
Thermal Resistance
Parameter
[11]
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
FBGA
39.3
9.69
TSOP II
35.62
9.13
Unit
C
/ W
C
/ W
AC Test Loads and Waveforms
V
CC
OUTPUT
30 pF / 50 pF
R1
V
CC
GND
R2
10%
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT
V
2.50 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Unit
V
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for data retention
Data retention current
V
CC
= 1.5 V
CE
1
> V
CC
– 0.2 V or CE
2
< 0.2 V
or (BHE and BLE) > V
CC
0.2
V,
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V
Ind’l
Conditions
Min
1.5
–
Typ
[12]
–
–
Max
–
4
Unit
V
A
t
CDR
[11]
t
R
[13]
Chip deselect to data
retention time
Operation recovery time
0
55
–
–
–
–
ns
ns
Data Retention Waveform
[14]
V
CC
CE
1
or
BHE
.
BLE
V
CC
, min.
t
CDR
DATA RETENTION MODE
V
DR
> 1.5 V
V
CC
, min.
t
R
or
CE
2
Notes
11. Tested initially and after any design or process changes that may affect these parameters
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
13. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
s
or stable at V
CC(min.)
> 100
s.
14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05392 Rev. *J
Page 5 of 15
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