K4E171611D, K4E151611D
K4E171612D, K4E151612D
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K
Ref.), access time (-45, -5 0 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features
of this family. All of this family have CAS -before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-
refresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung
′
s advanced CMOS pro-
cess to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer,
personal computer and portable machines.
FEATURES
•
Part Identification
-
-
-
-
K4E171611D-J(T) (5V, 4K Ref.)
K4E151611D-J(T) (5V, 1K Ref.)
K4E171612D-J(T) (3.3V, 4K Ref.)
K4E151612D-J(T) (3.3V, 1K Ref.)
Unit : mW
5V
1K
540
504
468
4K
550
495
440
1K
825
770
715
• Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in plastic SOJ 400mil and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V
±0.3V
power supply (3.3V product)
•
Active Power Dissipation
Speed
4K
-45
-50
-60
360
324
288
3.3V
•
Refresh Cycles
Part
NO.
K4E171611D
K4E171612D
K4E151611D
K4E151612D
V
CC
5V
3.3V
5V
3.3V
1K
16ms
Refresh
cycle
4K
Refresh period
Nor-
64ms
128ms
L-ver
RAS
UCAS
LCAS
W
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
VBB Generator
Refresh Timer
Refresh Control
Row Decoder
Sense Am ps & I/O
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
•
Performance Range
Speed
-45
-50
-60
Refresh Counter
Memory Array
1,048,576 x16
Cells
OE
DQ
8
to
DQ15
t
RAC
45ns
50ns
60ns
t
CAC
13ns
15ns
17ns
t
RC
69ns
84ns
104ns
t
HPC
16ns
20ns
25ns
Remark
5V/3.3V
5V/3.3V
5V/3.3V
A0-A11
(A0 - A9)
*1
A0 - A7
(A0 - A9)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note)
*1
:
1K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
K4E171611D, K4E151611D
K4E171612D, K4E151612D
CMOS DRAM
PIN CONFIGURATION
(Top Views)
• K4E17(5)1611(2)D-J
• K4E17(5)1611(2)D-T
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
C C
DQ0
DQ1
DQ2
DQ3
V
C C
DQ4
DQ5
DQ6
DQ7
N.C
N.C
N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0
A1
A2
A3
V
C C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
N.C
N.C
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V
SS
*A10 and A11 are N.C for K4E151611(2)D(5V/3.3V,
1K Ref.
product)
J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
Pin Name
A0 - A11
A0 - A9
DQ0 - 15
V
SS
RAS
UCAS
LCAS
W
OE
V
C C
N.C
Pin Function
Address Inputs (4K Product)
Address Inputs (1K Product)
Data In/Out
Ground
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
Data Output Enable
Power(+5V)
Power(+3.3V)
No Connection
K4E171611D, K4E151611D
K4E171612D, K4E151612D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
3.3V
V
IN,
V
O U T
V
CC
Tstg
P
D
I
OS
Address
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
1
50
Rating
CMOS DRAM
Units
5V
-1.0 to +7.0
-1.0 to +7.0
-55 to +150
1
50
V
V
°C
W
mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T
A
= 0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
Min
V
C C
V
SS
V
I H
V
IL
3.0
0
2.0
-0.3
*2
3.3V
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3
*1
0.8
Min
4.5
0
2.4
-1.0
*2
5V
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1.0
*1
0.8
V
V
V
V
Units
*1 : V
C C
+1.3V/15ns(3.3V), V
CC
+2.0V/20ns(5V), Pulse width is measured at V
C C
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V
SS
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Max
Parameter
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.3V,
all other input pins not under test=0 Volt)
3.3V
Output Leakage Current
(Data out is disabled, 0V
≤V
OUT
≤V
C C
)
Output High Voltage Level(I
O H
=-2mA)
Output Low Voltage Level(I
OL
=2mA)
Input Leakage Current (Any input 0≤V
IN
≤V
IN
+0.5V,
all other input pins not under test=0 Volt)
5V
Output Leakage Current
(Data out is disabled, 0V
≤V
OUT
≤V
C C
)
Output High Voltage Level(I
O H
=-5mA)
Output Low Voltage Level(I
OL
=4.2mA)
Symbol
I
I(L)
Min
-5
Max
5
Units
uA
I
O(L)
V
O H
V
OL
I
I(L)
-5
2.4
-
-5
5
-
0.4
5
uA
V
V
uA
I
O(L)
V
O H
V
OL
-5
2.4
-
5
-
0.4
uA
V
V
K4E171611D, K4E151611D
K4E171612D, K4E151612D
DC AND OPERATING CHARACTERISTICS
(Continued)
Symbol
Power
Speed
-45
-5 0
-6 0
Don′t care
-45
-5 0
-6 0
-45
-5 0
-6 0
Don′t care
-45
-5 0
-6 0
Don′t care
Don′t care
Max
K4E171612D
100
90
80
1
1
100
90
80
110
100
90
0.5
200
100
90
80
300
150
K4E151612D
150
140
130
1
1
150
140
130
110
100
90
0.5
200
150
140
130
200
150
K4E171611D
100
90
80
2
1
100
90
80
110
100
90
1
200
110
90
80
350
200
CMOS DRAM
K4E151611D
150
140
130
2
1
150
140
130
110
100
90
1
200
150
140
130
250
200
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
mA
mA
mA
uA
uA
I
C C 1
Don′t care
Normal
L
Don′t care
I
C C 2
I
C C 3
I
C C 4
Don′t care
Normal
L
Don′t care
L
L
I
C C 5
I
C C 6
I
C C 7
I
CCS
I
C C 1
* : Operating Current (RAS and UCAS, LCAS, Address cycling @t
RC
=min.)
I
C C 2
: Standby Current (RAS=UCAS=LCAS=W=V
IH
)
I
C C 3
* : RAS-only Refresh Current (UCAS=LCAS=V
IH
, RAS, Address cycling @t
R C
=min.)
I
C C 4
* : Hyper Page Mode Current (RAS=V
IL
, UCAS or LCAS, Address cycling @t
HPC
=min.)
I
C C 5
: Standby Current (RAS=UCAS=LCAS=W=V
CC
-0.2V)
I
C C 6
* : CAS-Before- RAS Refresh Current (RAS, UCAS or LCAS cycling @t
RC
=min.)
I
C C 7
: Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(V
IH
)=V
C C
-0.2V, Input low voltage(V
IL
)=0.2V, UCAS, LCAS=0.2V,
DQ=Don′t care, T
R C
=31.25us(4K/L-ver), 125us(1K/L-ver)
T
R A S
=T
RAS
min~300ns
I
C C S
: Self Refresh Current
RAS=UCAS =LCAS=V
IL
, W=OE=A0 ~ A11=V
C C
-0.2V or 0.2V,
DQ0 ~ DQ15=V
CC
-0.2V, 0.2V or Open
*Note :
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
, I
C C 3
and I
CC6,
address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Hyper page mode cycle time, t
HPC
.
K4E171611D, K4E151611D
K4E171612D, K4E151612D
CAPACITANCE
(T
A
=25°C, V
CC
=5V or 3.3V, f=1MHz)
Parameter
Input capacitance [A0 ~ A11]
Input capacitance [RAS , UCAS , LCAS, W, OE]
Output capacitance [DQ0 - DQ15]
Symbol
C
IN1
C
IN2
C
DQ
Min
-
-
-
CMOS DRAM
Max
5
7
7
Units
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
See note 1,2)
Test condition (5V device) : V
CC
=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V
Test condition (3.3V device) : V
C C
=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
* K4E151611D-TC(L)45 (5V, 1K Refresh) only
Symbol
Min
-45
Max
Min
84
115
45
14
23/*20
3
3
3
2
30
45
13
36
7 / *6.5
19
14
5
0
9
0
7
23
0
0
0
8
8
10
7
10K
31
22
10K
50
13
3
3
3
2
30
50
13
40
8
20
15
5
0
10
0
8
25
0
0
0
10
10
13
8
10K
35
25
10K
50
13
50
15
25
3
3
3
2
40
60
17
50
10
20
15
5
0
10
0
10
30
0
0
0
10
10
15
10
10K
43
30
10K
50
15
-50
Max
Min
104
140
60
17
30
-60
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
8
8
11
11
18
4
10
3,4,10
3,4,5
3,10
3
6,19
3
2
Units
Notes
t
R C
t
R W C
t
RAC
t
CAC
t
AA
t
CLZ
t
CEZ
t
OLZ
t
T
t
R P
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
W P
t
R W L
t
CWL
79
105
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