K4H560438J
K4H560838J
K4H561638J
DDR SDRAM
256Mb J-die DDR SDRAM Specification
66 TSOP-II
with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.12 August 2008
K4H560438J
K4H560838J
K4H561638J
DDR SDRAM
Table of Contents
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ..................................................................................................................4
3.0 Operating Frequencies ...............................................................................................................4
4.0 Pin Description ........................................................................................................................... 5
5.0 Package Physical Dimension ....................................................................................................6
6.0 Block Diagram (16Mb x 4 / 8Mb x 8 / 4Mb x 16 I/O x4 Banks) .................................................7
7.0 Input/Output Function Description ............................................................................................8
8.0 Command Truth Table ................................................................................................................9
9.0 General Description ..................................................................................................................10
10.0 Absolute Maximum Rating .....................................................................................................10
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
DC Operating Conditions .......................................................................................................10
DDR SDRAM Spec Items & Test Conditions ........................................................................11
Input/Output Capacitance ......................................................................................................11
Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
DDR SDRAM IDD spec table ..................................................................................................13
AC Operating Conditions .......................................................................................................14
AC Overshoot/Undershoot specification for Address and Control Pins ...........................14
Overshoot/Undershoot specification for Data, Strobe and Mask Pins ..............................15
AC Timming Parameters & Specifications ...........................................................................16
System Characteristics for DDR SDRAM .............................................................................17
Component Notes ...................................................................................................................18
22.0 System Notes ..........................................................................................................................20
23.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
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Rev. 1.12 August 2008
K4H560438J
K4H560838J
K4H561638J
DDR SDRAM
Year
2007
2007
2008
2008
- Release revision 1.0 SPEC
- Revised typo of package dimension
- Added Package pin out lead width
- Corrected typo
History
Revision History
Revision
1.0
1.1
1.11
1.12
Month
September
November
March
August
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K4H560438J
K4H560838J
K4H561638J
1.0 Key Features
• V
DD
: 2.5V ± 0.2V, V
DDQ
: 2.5V ± 0.2V for DDR266, 333
• V
DD
: 2.6V ± 0.1V, V
DDQ
: 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
Lead-Free & Halogen-Free
package
•
RoHS compliant
DDR SDRAM
2.0 Ordering Information
Part No.
K4H560438J-LC/LB3
K4H560438J-LC/LB0
K4H560838J-LC/LCC
K4H560838J-LC/LB3
K4H561638J-LC/LCC
K4H561638J-LC/LB3
Org.
64M x 4
32M x 8
16M x 16
Max Freq.
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Interface
SSTL2
SSTL2
SSTL2
Package
66pin TSOP II
Lead-Free & Halogen-Free
66pin TSOP II
Lead-Free & Halogen-Free
66pin TSOP II
Lead-Free & Halogen-Free
Note
1, 2
2
2
1, 2
2
1, 2
Note
1. "-B3"(DDR333, CL=2.5) can support "-B0"(DDR266, CL=2.5)/ "-A2"(DDR266, CL=2).
2. “L” of Part number(12th digit) stands for RoHS compliant and Halogen-Free product.
3.0 Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2.0)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
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4.0 Pin Description
16Mb x 16
32Mb x 8
64Mb x 4
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
6
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
DDR SDRAM
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
Bank Address
BA0~BA1
Auto Precharge
A10
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
256Mb TSOP-II Package Pinout
Organization
64Mx4
32Mx8
16Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
A0-A8
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
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Rev. 1.12 August 2008
Embedded System
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