8434013E-000NBG datasheet, PDF

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8434013E-000NBG: DescriptionPLL/Frequency Synthesis Circuit; CategoryAnalog mixed-signal IC The signal circuit; File Size2MB，95 Pages; ManufacturerIDT (Integrated Device Technology)

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8434013E-000NBG Overview

PLL/Frequency Synthesis Circuit

8434013E-000NBG Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
package instruction	,
Reach Compliance Code	compliant

8434013E-000NBG Preview

Port Synchronizer for IEEE 1588

Frequency and Time/Phase

Datasheet

8A34013

Overview

The 8A34013 is a port synchronizer for frequency and time/phase

for equipment that uses packet-based and physical layer-based

equipment synchronization.

The 8A34013 is a highly integrated device that provides tools to

manage timing references, clock sources, and timing paths for

IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The

PLL channels can act independently as frequency synthesizers,

jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital

Phase Lock Loops (DPLL).

▪

differential /

single-ended clock inputs

Clocks (T-TSCs) according to ITU-T G.8273.2

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▪

10Gb, 40Gb, and 100Gb Ethernet interfaces

▪

Central Office Timing Source and Distribution

▪

Wireless infrastructure for 4.5G and 5G network equipment

Features

▪

Four independent timing channels

•

Digitally Controlled Oscillator (DCO), or Digital Phase Lock

Loop (DPLL)

DPLL Digital Loop Filters (DLFs) are programmable with cut

off frequencies from 17Hz to 22kHz

Switching between DPLL and DCO modes is hitless and

dynamic

Generates output frequencies that are independent of input

frequencies via a Fractional Output Divider (FOD)

Each FOD supports output phase tuning with 1ps resolution

•

Each can act as a frequency synthesizer, jitter attenuator,

▪

4 Differential / 8 LVCMOS outputs

•

Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)

•

Jitter below 150fs RMS (10kHz to 20MHz)

•

LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL

•

output modes supported

Differential output swing is selectable: 400mV / 650mV /

800mV / 910mV

Independent output voltages of 3.3V, 2.5V, or 1.8V

▪

LVCMOS additionally supports 1.5V or 1.2V

•

The clock phase of each output is individually programmable

in 1ns to 2ns steps with a total range of ±180°

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Core and access IP switches / routers

▪

Synchronous Ethernet equipment

▪

Telecom Boundary Clocks (T-BCs) and Telecom Time Slave

▪

Automatic reference selection state machines select the active

reference for each DPLL based on the reference monitors,

priority tables, revertive / non-revertive, and other

programmable settings

to 54MHz or from a crystal oscillator

virtually any frequency from 1MHz to 150MHz

Time Protocol (PTP) / IEEE 1588 clocks

▪

System APLL operates from fundamental-mode crystal: 25MHz

▪

System DPLL accepts an XO, TCXO, or OCXO operating at

▪

DPLLs can be configured as DCOs to synthesize Precision

•

DCOs generate PTP based clocks with frequency resolution

less than 1.11

10

-16

Converters (TDC) with precision below 1ps

▪

DPLL Phase detectors can be used as Time-to-Digital

▪

Supports 1MHz I

C or 50MHz SPI serial processor ports

▪

Can configure itself automatically after reset via:

•

Internal Customer-programmable One-Time Programmable

memory with up to 16 different configurations

•

Standard external I

C EPROM via separate I

C Master Port

▪

1149.1 JTAG Boundary Scan

▪



7 mm 48-VFQFPN package

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Typical Applications

Redundant inputs frequency independent of each other

Any input can be designated as external frame/sync pulse of

EPPS (even pulse per second), 1PPS (Pulse per Second),

5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz

associated with a selectable reference clock input

•

Per-input programmable phase offset of up to ±1.638s in

1ps steps

▪

Reference monitors qualify/disqualify references depending on

LOS, activity, frequency monitoring, and/or LOS input pins

•

Loss of Signal (LOS) input pins (via GPIOs) can be assigned

to any input clock reference

•

Support frequencies from 1kHz to 1GHz

Any input can be mapped to any or all of the timing channels

June 17, 2019

8A34013 Datasheet

Block Diagram

Figure 1. Block Diagram

XO_DPLL

System

DPLL

FOD

To FODs

OSCI OSCO

Osc

System

APLL

Combo Bus

(Frequency Data)

Reference

Monitors

Reference

Switching

State

Machines

PWM

Decoders

DPLL /

DCO_4

DPLL /

DCO_5

DPLL /

DCO_6

DPLL /

DCO_7

DPLL /

DCO_2

FOD

ToD

Div

Q10

Q11

CLK0

CLK1

SPI/I

Status and Configuration

Registers

C Master

The 8A34013 supports multiple independent timing paths that can each be configured as a DPLL or as a DCO. Input-to-input,

input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly

synchronize interfaces such as 100GBASE-R, 40GBASE-R, 10GBASE-R, and 10GBASE-W and lower-rate Ethernet interfaces; as well

as SONET/SDH and PDH interfaces, and IEEE 1588 Time Stamp Units (TSUs).

The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The

output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL

reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal

connected between the OSCI and OSCO pins.

The System DPLL generates an internal system clock that is used by the reference monitors and other digital circuitry in the device. If the

reference provided to the System APLL meets the stability and accuracy requirements of the intended application then the System DPLL

can free run and a System DPLL reference is not required. Alternatively, the System DPLL can be locked to an external reference that

meets the stability and accuracy requirements of the intended application. The System DPLL can accept a reference from the XO_DPLL

pin or via the reference selection mux.

The 8A34013 is a port synchronizer for frequency and time/phase for equipment that uses packet based and physical layer based

equipment synchronization. The 8A34011 is a highly integrated device that provides tools to manage timing references, clock sources,

and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The PLL channels can act independently as frequency

synthesizers, jitter attenuators, Digitally Controlled Oscillators (DCO), or Digital Phase Lock Loops (DPLL).

Description

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OTP

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PWM

Encoders

GPIO / JTAG

June 17, 2019

8A34013 Datasheet

The frequency accuracy/stability of the internal system clock determines the frequency accuracy/stability of the DPLLs in Free-Run mode

and in Holdover mode; and it affects the wander generation of the DPLLs in Locked and DCO modes. When provided with a suitably

stable and accurate system clock, the DPLLs meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise tolerance,

transient response, and holdover performance requirements of ITU-T G.8262 synchronous Ethernet Equipment Clock (EEC) options 1

and 2.

The 8A34013 accepts up to two differential reference inputs and up to four single-ended reference inputs that can operate at common

GNSS, Ethernet, SONET/SDH, PDH frequencies, and any input frequency from 1kHz to 1GHz (250MHz in single-ended mode). The

references are continually monitored for loss of signal and for frequency offset per user-programmed thresholds. All of the references are

available to all the DPLLs. The active reference for each DPLL is determined by forced selection or by automatic selection based on user

programmed priorities, locking allowances, reference monitors, revertive and non-revertive settings, and LOS inputs.

The 8A34013 can accept a clock reference and an associated frame pulse or sync signal as a pair. DPLLs can lock to the clock reference

and align the sync and clock outputs with the paired sync/frame input. The device allows any of the reference inputs to be configured as

sync inputs that can be associated with any of the other reference inputs. The input sync signals can have a frequency of 1PPS (Pulse

per Second), EPPS (even pulse per second), 5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8 kHz. This feature enables any

DPLL to phase align its frame sync and clock outputs with a sync input without the need to use a low bandwidth setting to lock directly to

the sync input.

The 8A34013 generates up to four differential output clocks at any frequency from 0.5Hz to 1GHz. The differential outputs can support

LVPECL, LVDS, HCSL, and CML. It generates up to eight single-ended clocks with frequencies from 0.5Hz to 250MHz. LVCMOS output

supports 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V. Each output stage can be independently configured.

Clocks generated by the 8A34013 have jitter below 150fs RMS (10kHz to 20MHz) and therefore are suitable for serial 100GBASE-R,

40GBASE-R, and lower rate interfaces.

All control and status registers are accessed through the I

C / SPI slave microprocessor interface, the SPI interface mode supports high

clock rates (up to 50MHz). For configuring the DPLLs, the I

C master interface can automatically load a configuration from an external

EEPROM after reset. The 8A34013 also has an internal customer-programmable One-Time Programmable memory with up to 16

different configurations.

In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, any of the DPLLs can be configured as an EEC/SEC to

output clocks for the T0 reference point and can be used to output clocks for the T4 reference point.

For applications per ITU-T G.8263, any DPLL can be configured as a DCO to synthesize packet-based clocks.

In Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per ITU-T G.8275.2, two DPLLs can be used;

one DPLL is configured as a DCO to synthesize PTP clocks and the other DPLL is configured as an EEC/SEC to generate physical layer

clocks. Combo mode provides physical layer frequency support from the EEC/SEC to the PTP clock.

The DPLLs can be configured with a range of selectable filtering bandwidths from 17Hz to 22kHz for use in jitter attenuation and rate

conversion applications.

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The DPLLs support four primary operating modes: Free-Run, Locked, Holdover, and DCO. In Free-Run mode the DPLLs synthesize

clocks based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. Additionally

in Locked mode, the long-term output frequency accuracy is the same as the long-term frequency accuracy of the selected input

reference. In Holdover mode, the DPLL uses frequency data acquired while in Locked mode to generate accurate frequencies when input

references are not available. In DCO mode the DPLL control loop is opened and the DCO can be controlled by a PTP clock recovery

servo running on an external processor to synthesize PTP clocks.

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8A34013 Datasheet

Contents

Overview .............................................................................................................................................................................................................. 1

Typical Applications.............................................................................................................................................................................................. 1

Features ............................................................................................................................................................................................................... 1

Block Diagram ...................................................................................................................................................................................................... 2

Description ............................................................................................................................................................................................................ 2

Pin Assignments................................................................................................................................................................................................... 9

Pin Descriptions and Pin Characteristics ............................................................................................................................................................. 9

Overview of the 8A3xxxx Family ........................................................................................................................................................................ 13

Functional Description........................................................................................................................................................................................ 13

Basic Functional Blocks of the 8A34013 ............................................................................................................................................................ 14

Crystal Input (OSCI / OSCO) ...................................................................................................................................................................... 14

Frequency Representation in 8A34013............................................................................................................................................. 14

System Analog PLL (APLL) ........................................................................................................................................................................ 14

Input Stage.................................................................................................................................................................................................. 15

Reference Monitoring.................................................................................................................................................................................. 17

Loss of Signal (LOS) Monitoring........................................................................................................................................................ 17

Activity ............................................................................................................................................................................................... 18

Timer ................................................................................................................................................................................................. 19

Frequency Offset Monitoring ............................................................................................................................................................. 19

Advanced Input Clock Qualification ............................................................................................................................................................ 20

Input Clock Qualification.................................................................................................................................................................... 20

Clock Reference Disqualifier through GPIO...................................................................................................................................... 20

Frame Pulse Operation............................................................................................................................................................................... 20

Sync Pulse Operation ................................................................................................................................................................................. 21

Crystal Oscillator Input (XO_DPLL) ............................................................................................................................................................ 22

Digital Phase Locked Loop (DPLL)............................................................................................................................................................. 22

Free-Run Mode ................................................................................................................................................................................. 24

Locked Mode..................................................................................................................................................................................... 24

Holdover Mode .................................................................................................................................................................................. 24

Manual Holdover Mode ..................................................................................................................................................................... 24

External Feedback............................................................................................................................................................................. 25

DPLL Input Clock Qualification and Selection............................................................................................................................................. 25

Automatic Input Clock Selection........................................................................................................................................................ 26

Manual Input Clock Selection via Register or GPIO.......................................................................................................................... 26

Slave or GPIO Slave Selection.......................................................................................................................................................... 26

DPLL Switchover Management................................................................................................................................................................... 26

Revertive and Non-Revertive Switching............................................................................................................................................ 26

Hitless Reference Switching.............................................................................................................................................................. 26

Phase Slope Limiting......................................................................................................................................................................... 27

DPLL Frequency Offset Limit Setting ................................................................................................................................................ 27

DPLL Fast Lock Operation.......................................................................................................................................................................... 27

Steerable Fractional Output Divider (FOD)................................................................................................................................................. 28

FOD Multiplexing and Output Stages.......................................................................................................................................................... 29

Integer Output Divider ....................................................................................................................................................................... 30

Output Duty Cycle Adjustment .......................................................................................................................................................... 30

Output Coarse Phase Adjustment..................................................................................................................................................... 30

Output Buffer ..................................................................................................................................................................................... 31

General Purpose Input/Outputs (GPIOs) .................................................................................................................................................... 32

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June 17, 2019

8A34013 Datasheet

GPIO Modes...................................................................................................................................................................................... 32

GPIO Pin Configuration..................................................................................................................................................................... 33

Alarm Output Operation..................................................................................................................................................................... 33

Device Initial Configuration ......................................................................................................................................................................... 35

Use of GPIO Pins at Reset................................................................................................................................................................ 35

Default Values for Registers.............................................................................................................................................................. 36

One-Time Programmable (OTP) Memory................................................................................................................................................... 36

Configuration Data in OTP ................................................................................................................................................................ 37

Use of External I

C EEPROM..................................................................................................................................................................... 37

Device Updates in External I

C EEPROM ........................................................................................................................................ 37

Configuration Data in External I2C EEPROM ................................................................................................................................... 38

Reset Sequence.......................................................................................................................................................................................... 38

Step 0 – Reset Sequence Starting Condition.................................................................................................................................... 38

Step 1 – Negation of nMR (Rising Edge) .......................................................................................................................................... 39

Step 2 – Internally Set Default Conditions......................................................................................................................................... 39

Step 3 – Scan for Device Updates in EEPROM................................................................................................................................ 39

Step 4 – Read Configuration from OTP............................................................................................................................................. 39

Step 5 – Search for Configuration in External EEPROM................................................................................................................... 39

Step 6 - Load OTP Hotfix and Execute ............................................................................................................................................. 39

Step 7 – Complete Configuration ...................................................................................................................................................... 40

Clock Gating and Logic Power-Down Control............................................................................................................................................. 40

Serial Port Functions................................................................................................................................................................................... 40

Addressing Registers within the 8A34013......................................................................................................................................... 41

I2C Slave Operation .......................................................................................................................................................................... 42

I2C Master......................................................................................................................................................................................... 44

SPI Operation.................................................................................................................................................................................... 45

JTAG Interface............................................................................................................................................................................................ 48

Basic Operating Modes (Synthesizer / Clock Generator / Jitter Attenuator) ...................................................................................................... 49

Free-Running Synthesizer Operation.......................................................................................................................................................... 49

Clock Generator Operation ......................................................................................................................................................................... 49

Synthesizer Disciplined with Oscillator Operation....................................................................................................................................... 50

Jitter Attenuator Operation.......................................................................................................................................................................... 50

Jitter Attenuator Operation with External Digital Loop Filter ....................................................................................................................... 51

Jitter Attenuator Disciplined with Oscillator Operation ................................................................................................................................ 51

Digitally-Controlled Oscillator Operation via External Control..................................................................................................................... 52

Write-Frequency Mode...................................................................................................................................................................... 52

Increment / Decrement Registers and Pins....................................................................................................................................... 53

Write-Phase Mode............................................................................................................................................................................. 53

Adjusting Phase while in Closed Loop Operation ....................................................................................................................................... 54

Combo Mode............................................................................................................................................................................................... 54

Time-of-Day (ToD) Operation ..................................................................................................................................................................... 56

ToD Triggers and Latches................................................................................................................................................................. 56

GPIO Functions Associated with ToD Operation .............................................................................................................................. 58

Pulse-Width Modulation Encoders, Decoders, and FIFO ........................................................................................................................... 58

PWM Signature ................................................................................................................................................................................. 59

PWM Frames..................................................................................................................................................................................... 59

1PPS and ToD Distribution (PWM_PPS) .......................................................................................................................................... 60

Multi-Clock Distribution (PWM_SYNC).............................................................................................................................................. 60

Register Read/Write (PWM_READ/PWM_WRITE)........................................................................................................................... 61

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June 17, 2019

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8434013E-000NBG Related Products

	8434013E-000NBG	8434013E-000NBG8	8434013E-000NBG#	8434013E-DDDNBG8	8434013E-DDDNBG#
Description	PLL/Frequency Synthesis Circuit	PLL/Frequency Synthesis Circuit	PLL/Frequency Synthesis Circuit	PLL/Frequency Synthesis Circuit	PLL/Frequency Synthesis Circuit
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant

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