XR-T6166
...the analog plus company
TM
Codirectional Digital Data
Processor
June 1997–3
FEATURES
D
Low Power CMOS Technology
D
All Receiver and Transmitter Inputs and Outputs are
TTL Compatible
D
Transmitter Inhibits Bipolar Violation Insertion for
Transmission of Alarm Conditions
D
Alarm Output Indicates Loss of Received Bipolar
Violations
D
Tolerance of 125µs Variance of Data Transfer
Timing in Both Transmit and Receive Paths
Allows Operation in Plesiochronous Networks
D
Both Receiver and Transmitter Perform Byte
Insertion or Deletion in Response to Local Clock
Slips and Provide Outputs Indicating Slip Logic
Activity
APPLICATIONS
D
CCITT G.703 Compliant 64kbps Codirectional
Interface
D
Performs the Digital and Analog Functions for
a Complete 64kbps Data Adaption Unit (DAU) When
Used With the XR-T6164
GENERAL DESCRIPTION
The XR-T6166 is a CMOS device which contains the
digital circuitry necessary to interface both directions of a
64kbps data stream to 2.048Mbps transmit and receive
PCM time-slots. The XR-T6166 and the companion
XR-T6164 line interface chip together form a CCITT
G.703 compliant 64kbps codirectional interface.
The XR-T6166 contains separate transmit and receive
sections. The transmitter transforms 8 bit serial data from
a 2.048Mbps time-slot into an encoded 64kbps data
ORDERING INFORMATION
Operating
Temperature Range
0°C to +70°C
–40°C to 85°C
0°C to +70°C
–40°C to 85°C
stream. The receiver, which performs the reverse
operation, decodes the 64kbps data, extracts a clock
signal, and then outputs the data to a 2.048Mbps
time-slot. The XR-T6166 provides features which allow
the repetitions and deletions of both received and
transmitted data as clock skews and transients occur.
These slip occurrences are indicated by byte insertion
and deletion flags. Outputs are also provided for
extracted receive clock and clock recovery circuit loss of
lock.
Part No.
XR-T6166CP
XR-T6166IP
XR-T6166CD
XR-T6166ID
Package
28 Lead 600 Mil PDIP
28 Lead 600 Mil PDIP
28 Lead 300 Mil JEDEC SOIC
28 Lead 300 Mil JEDEC SOIC
Rev. 2.02
E1990
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538
z
(510) 668-7000
z
(510) 668-7010
1
XR-T6166
PCMIN
TX2MHz
TS1T
TS2T
TTSEL
19
D
20
8 Bit Input Register
CLK
8
Byte
Deletion
10
11
BDT
12
time-slot
Mux
8 Bit Latch
Load
8
CLK
8 Bit Output Register
Load
Q
Byte
Insertion
18
15
BIT
Control
Circuitry
TX256kHz
17
Octet
Counter
Violation
Insertion
Coding
Logic
D
CLK
Q
D
CLK
Q
13
T+R
ALARMIN
16
14
T-R
Figure 1. XR-T6166 Transmitter Section Block Diagram
Byte Sync
Detection
CLK
S+R
S-R
2
Violation
Loss
Alarm
Data
Decoder
CLK
1
ALARM
3
BLS
4
D
RX2MHz
TS1R
TS2R
RTSEL
5
Q
28
23
time-slot
Mux
Time
Slot
Mux
Register
Select
Logic
8 Bit Reg 0
CLK
D
Q
8 Bit Reg 1
CLK
REG 0 SEL
REG 1 SEL
time-slot
PCMOUT
24
27
Byte
Insertion
26
BIR
BLANK
6
Byte
Deletion
128kHz Recovered Clock
25
BDR
RXCK2MHz
9
Clock
Recovery
7
RXCKOUT
CS
22
Figure 2. XR-T6166 Receiver Section Block Diagram
Rev. 2.02
2
XR-T6166
PIN CONFIGURATION
ALARM
S+R
S-R
BLS
RX2MHz
BLANK
RXCKOUT
V
DD
RXCK2MHz
TS1T
BDT
TS2T
T+R
T-R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCMOUT
RTSEL
BIR
BDR
TS2R
TS1R
CS
V
SS
TX2MHz
PCMIN
BIT
TX256kHz
ALARMIN
TTSEL
ALARM
S+R
S-R
BLS
RX2MHz
BLANK
RXCKOUT
V
DD
RXCK2MHz
TS1T
BDT
TS2T
T+R
T-R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PCMOUT
RTSEL
BIR
BDR
TS2R
TS1R
CS
V
SS
TX2MHz
PCMIN
BIT
TX256kHz
ALARMIN
TTSEL
28 Lead PDIP (0.600”)
28 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
ALARM
S+R
S-R
BLS
RX2MHz
BLANK
RXCKOUT
V
DD
RXCK2MHz
TS1T
BDT
TS2T
T+R
T-R
TTSEL
ALARMIN
I
I
O
I
O
O
I
I
Type
O
I
I
I
I
I
O
Description
Octet Timing Alarm.
When active, indicates loss of received bipolar violations that are used
for octet timing. Active high.
Positive AMI Data to Receiver.
Positive data from the XR-T6164 receive-side. Active low.
Negative AMI Data to Receiver.
Negative data from the XR-T6164 receive-side. Active low.
Byte Locking Supervision.
When active, causes blanking of PCMOUT under received
alarm conditions. Active low.
Receiver 2.048MHz Clock.
Used to clock out PCM data.
PCMOUT Data Blanking.
When active, forces PCMOUT data to all ones (AIS). Active high.
128kHz Extracted Clock.
Clock recovered from received data.
+5V
$10%
Power Source.
2.048MHz Clock.
Used by receiver clock recovery circuit.
Transmitter Time-slot 1 Input.
Transmitter Byte Deletion Flag.
Active when a transmit byte is deleted. Active high.
Transmitter Time-slot 2 Input.
Transmit Positive AMI Data Output.
Data to XR-T6164 positive transmitter input. Active low.
Transmit Negative AMI Data Output.
Data to XR-T6164 negative transmitter input. Active
low.
Transmit Time-slot Select.
When high, pin 10 is selected; when low, pin 12 is selected.
Alarm Input.
When active, inhibits insertion of violations used for octet timing in transmitter
output. Active high.
Rev. 2.02
3
XR-T6166
PIN DESCRIPTION (CONT’D)
Pin #
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
TX256kHz
BIT
PCMIN
TX2MHz
V
SS
CS
TS1R
TS2R
BDR
BIR
RTSEL
PCMOUT
O
I
I
O
O
I
O
Type
I
O
I
I
Description
Transmitter 256kHz Clock.
Used to output 64kbps encoded data.
Transmitter Byte Insertion Flag.
Active when a transmit byte is repeated. Active high.
Transmitter PCM Input.
Data read from the system PCM bus.
Transmitter 2.048MHz Clock.
Clocks PCM data in PCMIN.
Ground.
Clock Seek.
Indicates that clock recovery circuit has loss of lock with received data. Active
high.
Receiver Time-slot 1 Input.
Receiver Time-slot 2 Input.
Receiver Byte Deletion Flag.
Active when received data byte is deleted. Active high.
Receiver Byte Insertion Flag.
Active when a received data byte is repeated. Active high.
Receive Time-slot Select.
When high, pin 23 is selected; when low, pin 24 is selected.
Received PCM Output Data.
Data sent to the system PCM bus.
Rev. 2.02
4
XR-T6166
ELECTRICAL CHARACTERISTICS
Test Conditions: V
DD
= 5V
$10%,
T
A
= 25°C, Unless Otherwise Specified
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
DC Electrical Characteristics
V
IH
V
IL
V
DD
I
DD
I
IL
V
OL
V
OH
AC Electrical Characteristics
General
tr, tf
Receiver
tRS
tRH
tDRS
tDRH
tRXD
RX2MHz Rising Edge to TS
Rising Edge Set Up Time
RX2MHz Rising Edge to TS
Falling Edge Hold Time
TS Rising Edge to Leading Edge
of PCMOUT D0 Bit Delay
TS Falling Edge to Trailing Edge
of PCMOUT D7 Bit Hold Time
RX2MHz Rising Egde to
PCMOUT Bits D1 Through D6
Rising Edge Delay
PCMOUT Pulse Width
RX2MHz High Time
RX2MHz Low Time
RX2MHz Period
488
244
244
488
0
0
0
tRXL-
100
tRXL-
100
10
10
10
ns
ns
ns
ns
ns
Output Rise/Fall Time
20
ns
All Outputs
2.4
Logic 1
Logic 0
Supply
Supply Current
Input Leakage
4.5
500
1
0.4
2.4
0.4
5.5
V
V
V
µA
µA
V
mA
At 1.6mA
At 0.4mA
Dynamic Supply Current
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
tPW
tRXH
tRXL
tRXCLK
Transmitter
tTS
tTH
tDS
tDH
tTXH
tTXL
tTXCLK
Rev. 2.02
ns
ns
ns
ns
Figure 3
Figure 3
Figure 3
$100ppm
TS Rising Edge to TX2MHz Set
Up Time
TS Falling Edge to TX2MHz Hold
Time
PCMIN Edge to TX2MHz Set Up
Time
PCMIN Edge to TX2MHz Hold
Time
TX2MHz High Time
TX2MHz Low Time
TX2MHz Period
20
0
100
100
244
244
488
tTXL-
100
tTXL-
100
ns
ns
ns
ns
ns
ns
ns
Figure 5
Figure 5
Figure 5
Figure 5
Figure 5
Figure 5
$100ppm
5
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