STK14CA8
128K x 8
AutoStore
nvSRAM
TM
QuantumTrap
CMOS
Nonvolatile Static RAM
FEATURES
•
25ns, 35ns and 45ns Access Times
•
“Hands-off” Automatic
STORE
on Power Down
with only a small capacitor
•
STORE
to
QuantumTrap™
Nonvolatile
Elements is Initiated by Software , device pin
or
AutoStore™
on Power Down
•
RECALL
to SRAM Initiated by Software or
Power Up
•
Unlimited
READ, WRITE
and
RECALL
Cycles
•
5mA Typical I
CC
at 200ns Cycle Time
•
1,000,000
STORE
Cycles to
QuantumTrap™
•
100-Year Data Retention to
QuantumTrap™
•
Single 3V +20%, -10% Operation
•
Commercial and Industrial Temperatures
•
SOIC, SSOP and DIP Packages
•
RoHS Compliance
TM
DESCRIPTION
The Simtek STK14CA8 is a fast static RAM with a
nonvolatile element in each memory cell. The
embedded
nonvolatile
elements
incorporate
TM
Simtek’s
QuantumTrap
technology producing the
world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles,
while independent, nonvolatile data resides in the
TM
highly reliable
QuantumTrap
cell. Data transfers
from the SRAM to the nonvolatile elements (the
STORE
operation) takes place automatically at
power down. On power up, data is restored to the
SRAM (the
RECALL
operation) from the nonvolatile
memory. Both the
STORE
and
RECALL
operations
are also available under software control.
BLOCK DIAGRAM
Quantum Trap
1024 X 1024
ROW DECODER
STORE
STATIC RAM
ARRAY
1024 X 1024
RECALL
V
CC
V
CAP
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
A
15
– A
0
A
0
A
1
A
2
A
3
A
4
A
10
A
11
G
E
W
Figure 1. Block Diagram
December 2004
1
Document Control #ML0022 rev 1.0
STK14CA8
PACKAGES
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
A
15
HSB
W
A
13
A
8
A
9
A
11
V
CAP
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
HSB
W
A
13
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
V
SS
V
SS
DQ
0
A
3
A
2
A
1
A
0
DQ
1
DQ
2
48 Pin SSOP
Relative PCB area usage.
See website for detailed
package size specifications.
PIN DESCRIPTIONS
Pin Name
A
16
– A
0
DQ
7
–DQ
0
E
W
G
V
CC
HSB
I/O
Input
I/O
Input
Input
Input
Power Supply
I/O
Description
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
Chip Enable: The active low E
Write Enable: The active low W
the falling edge of E .
Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G
high causes the DQ pins to tri-state.
Power 3.0V +20%, -10%
Hardware Store Busy: When low this output indicates a Hardware Store is in progress. When pulled low external
to the chip it will initiate a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not
connected. (Connection Optional)
V
CAP
V
SS
(Blank)
Power Supply
Power Supply
No Connect
Autostore
Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile
elements.
Ground
Unlabeled pins have no internal connection.
input selects the device.
enables data on the DQ pins to be written to the address location latched by
December 2004
SSOP
DQ
6
G
A
10
E
DQ
7
DQ
5
DQ
4
DQ
3
V
CC
32 Pin
SOIC
or
PDIP
2
Document Control #ML0022 rev 1.0
STK14CA8
ABSOLUTE MAXIMUM RATINGS
a
-0.5V to +4.1V
Power Supply Voltage
-0.5V to (V
CC
+ 0.5V)
Voltage on Input Relative to V
SS
-0.5V to (V
CC
+ 0.5V)
Voltage on Outputs
Temperature under Bias
–55°C to 125°C
Junction Temperature
–55°C to 140°C
Storage Temperature
–65°C to 150°C
Power Dissipation
1W
DC Output Current (1 output at a time, 1s duration)
15mA
Notes
a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
Package Thermal Characteristics see website:
http://www.simtek.com/
DC CHARACTERISTICS
Symbol
I
CC1
Parameter
Average V
CC
Current
Commercial
MIN
MAX
65
55
50
Industrial
MIN
MAX
70
60
55
Units
mA
mA
mA
Notes
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care, V
CC
= max
Average current for duration of
STORE
cycle (t
STORE
).
W
≥
(V
CC
– 0.2V)
All Others Inputs Cycling, at CMOS Levels.
Dependent on output loading and cycle
rate. Values obtained without output loads.
All Inputs Don’t Care
Average current for duration of
STORE
cycle (t
STORE
).
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
Standby current level after nonvolatile
cycle is complete.
V
CC
= max
I
CC2
Average V
CC
Current during STORE
Average V
CC
Current at t
AVAV
= 200ns
3
3
mA
I
CC3
3V, 25°C, Typical
Average V
CAP
Current during
AutoStore™
Cycle
V
CC
Standby Current
5
3
5
3
mA
mA
I
CC4
I
SB
(Standby, Stable CMOS Input Levels)
2
2
mA
I
ILK
I
OLK
V
IH
V
IL
V
OH
V
OL
T
A
V
CC
V
CAP
Input Leakage Current
±1
Off-State Output Leakage Current
±1
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
Storage Capacitor
0
2.7
17
2.0
V
SS
– 0.5
2.4
0.4
70
3.6
57
–40
2.7
17
V
CC
+ 0.3
0.8
2.0
V
SS
– 0.5
2.4
0.4
85
3.6
57
±1
V
CC
+ 0.3
0.8
µA
V
V
V
V
o
±1
µA
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
All Inputs
All Inputs
I
OUT
= –2mA
I
OUT
= 4mA
C
3.0V +20%, -10%
Between Vcap pin and Vss, 5V rated.
V
µF
December 2004
3
Document Control #ML0022 rev 1.0
STK14CA8
AC TEST CONDITIONS
0V to 3V
Input Pulse Levels
Input Rise and Fall Times
≤
5ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figure 2 and Figure 3
CAPACITANCE
SYMBOL
C
IN
C
OUT
Notes
b
(T
A
= 25°C, f = 1.0MHz)
MAX
7
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
PARAMETER
Input Capacitance
Output Capacitance
b: These parameters are guaranteed but not tested
3.0V
577 Ohms
OUTPUT
789 Ohms
3.0V
577 Ohms
OUTPUT
30 pF
INCLUDING
SCOPE AND
FIXTURE
789 Ohms
5 pF
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 2. AC Output Loading
Figure 3. AC Output Loading,
for tristate specs (
t
HZ
, t
LZ
, t
WLQZ
, t
WHQZ
,
t
GLQX
, t
GHQZ
)
December 2004
4
Document Control #ML0022 rev 1.0
STK14CA8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
1
2
3
4
5
6
7
8
9
10
11
d
t
AXQX
c
t
AVAV
d
t
AVQV
STK14CA8-25
PARAMETER
Alt.
t
ACS
t
RC
t
AA
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
3
3
10
25
25
12
MIN
MAX
25
STK14CA8-35
MIN
MAX
35
35
35
15
3
3
13
0
13
0
35
STK14CA8-45
UNITS
MIN
MAX
45
45
45
20
3
3
15
0
15
0
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
#2
t
ELQV
c
t
AVAV
t
GLQV
t
OE
t
OH
t
ELQX
e
t
EHQZ
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
t
GLQX
e
t
GHQZ
t
ELICCb
b
t
EHICC
Notes
c: W must be high during SRAM READ cycles
d: Device is continuously selected with E and G both low
e: Measured
±
200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1:
Address Controlled
c,d,f
2
t
AVAV
ADDRESS
5
t
AXQX
3
t
AVQV
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
c,f
2
t
AVAV
ADDRESS
6
t
ELQX
7
t
EHQZ
1
t
ELQV
11
t
EHICCL
E
G
4
8
DQ (DATA OUT)
t
GLQX
10
t
ELICCH
I
CC
STANDBY
t
GLQV
9
t
GHQZ
DATA VALID
ACTIVE
December 2004
5
Document Control #ML0022 rev 1.0
京公网安备 11010802033920号
EEWORLD
