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WMS512K8-45FEIA

Description
512K X 8 STANDARD SRAM, 20 ns, CDFP36
Categorystorage   
File Size118KB,10 Pages
ManufacturerETC
Download Datasheet Parametric View All

WMS512K8-45FEIA Overview

512K X 8 STANDARD SRAM, 20 ns, CDFP36

WMS512K8-45FEIA Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals36
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
maximum access time20 ns
Processing package descriptionCERAMIC, DFP-36
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeFLATPACK
surface mountYes
Terminal formFLAT
terminal coatingGOLD
Terminal locationDUAL
Packaging MaterialsCERAMIC, METAL-SEALED COFIRED
Temperature levelINDUSTRIAL
memory width8
organize512K X 8
storage density4.19E6 deg
operating modeASYNCHRONOUS
Number of digits524288 words
Number of digits512K
Memory IC typeSTANDARD SRAM
serial parallelPARALLEL
WMS512K8-XXX
HI-RELIABILITY PRODUCT
512Kx8 MONOLITHIC SRAM, SMD 5962-95613
FEATURES
s
Access Times 15, 17, 20, 25, 35, 45, 55ns
s
MIL-STD-883 Compliant Devices Available
s
Revolutionary, Center Power/Ground Pinout
JEDEC Approved
• 36 lead Ceramic SOJ (Package 100)
• 36 lead Ceramic Flat Pack (Package 226)
s
Evolutionary, Corner Power/Ground Pinout
JEDEC Approved
• 32 pin Ceramic DIP (Package 300)
• 32 lead Ceramic SOJ (Package 101)
• 32 lead Ceramic Flat Pack (Package 220)
• 32 lead Ceramic Flat Pack (Package 142)
s
32 pin, Rectangular Ceramic Leadless Chip Carrier
(Package 601)
s
Commercial, Industrial and Military Temperature Range
s
5 Volt Power Supply
s
Low Power CMOS
s
Low Power Data Retention for Battery Back-up Operation
s
TTL Compatible Inputs and Outputs
REVOLUTIONARY PINOUT
36 FLAT PACK
36 CSOJ
EVOLUTIONARY PINOUT
32 DIP
32 CSOJ (DE)
32 FLAT PACK (FE)*
32 FLAT PACK (FD)
32 CLCC
TOP VIEW
A0
A1
A2
A3
A4
CS
I/O0
I/O1
V
CC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
TOP VIEW
A12
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
V
CC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
TOP VIEW
A14
A16
A18
A15
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
I/O
0
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O1
I/O2
V
SS
I/O3
I/O4
I/O5
I/O6
A17
V
CC
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
PIN DESCRIPTION
A
0-18
I/O
0-7
CS
OE
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
*Package not recommended for new designs, "FD" recommended for new designs.
October 2000 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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