Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
PHD108NQ03LT
N-channel TrenchMOS logic level FET
Rev. 04 — 5 June 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Simple gate drive required due to low
gate charge
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC convertors
Switched-mode power supplies
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
25
75
187
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
175 °C
drain current
total power
dissipation
Symbol Parameter
Avalance ruggedness
E
DS(AL)S
non-repetitive
drain-source
avalanche energy
Dynamic characteristics
Q
GD
gate-drain charge
V
GS
= 4.5 V; I
D
= 25 A;
V
DS
= 12 V; T
j
= 25 °C; see
Figure 12;
see
Figure 13
V
GS
= 10 V; I
D
= 25 A;
T
j
= 25 °C; see
Figure 10;
see
Figure 11
-
5.6
-
nC
V
GS
= 10 V; T
j(init)
= 25 °C;
I
D
= 43 A; V
sup
≤
25 V;
unclamped; t
p
= 0.25 ms;
R
GS
= 50
Ω
-
-
180
mJ
Static characteristics
R
DSon
drain-source
on-state resistance
-
5.3
6
mΩ
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol
G
D
S
D
Description
gate
drain
source
mounting base; connected to
drain
2
1
3
Simplified outline
[1]
mb
Graphic symbol
D
G
mbb076
S
SOT428
(SC-63; DPAK)
[1]
It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
PHD108NQ03LT
SC-63;
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
Version
SOT428
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 5 V; T
mb
= 25 °C; see
Figure 1;
see
Figure 3
V
GS
= 5 V; T
mb
= 100 °C; see
Figure 1
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
25
25
20
75
75
240
187
175
175
75
240
180
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalance ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 43 A; V
sup
≤
25 V;
drain-source avalanche unclamped; t
p
= 0.25 ms; R
GS
= 50
Ω
energy
PHD108NQ03LT_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 5 June 2009
2 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03ar58
120
P
der
(%)
80
03aa16
40
40
0
0
50
100
150
T
mb
(
°
C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
03ar59
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
= 10 µs
100
μ
s
DC
10
1 ms
10 ms
1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD108NQ03LT_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 5 June 2009
3 of 12
NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
0.8
Unit
K/W
thermal resistance from see
Figure 4
junction to mounting
base
thermal resistance from minimum footprint; mounted on a
junction to ambient
printed-circuit board; vertical in still air
mounted on a printed-circuit board;
vertical in still air; SOT404 minimum
footprint
R
th(j-a)
-
-
75
50
-
-
K/W
K/W
1
δ =
0.5
03ar60
Z
th(j-mb)
(K/W)
0.2
10
-1
0.1
0.05
P
δ
=
t
p
T
0.02
single pulse
t
p
t
T
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C; see
Figure 8;
see
Figure 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C; see
Figure 8;
see
Figure 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C; see
Figure 8;
see
Figure 9
I
DSS
I
GSS
drain leakage current
gate leakage current
V
DS
= 25 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 25 V; V
GS
= 0 V; T
j
= 175 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
PHD108NQ03LT_4
Min
25
22
1
0.5
-
-
-
-
-
Typ
-
-
1.5
-
-
-
-
0.02
0.02
Max
-
-
2
-
2.2
1
500
100
100
Unit
V
V
V
V
V
µA
µA
nA
nA
4 of 12
Static characteristics
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 5 June 2009
京公网安备 11010802033920号
EEWORLD
