K7D161874B-HC27 datasheet, PDF

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K7D161874B-HC27: Description512Kx36 & 1Mx18 SRAM; File Size454KB，17 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7D161874B-HC27 Overview

512Kx36 & 1Mx18 SRAM

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K7D163674B

K7D161874B

Document Title

16M DDR SYNCHRONOUS SRAM

512Kx36 & 1Mx18 SRAM

Revision History

Rev No.

Rev. 0.0

Rev. 0.1

History

Initial document.

Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS

-to support 1.8~2.5V V

, change some items.

Change DC CHARACTERISTICS (Stop Clock Standby Current)

-I

SB1

: 100 -> 150

Change JTAG Instruction Cording

- For Reserved

Change DC CHARACTERISTICS (Increase Operating Current)

- x36 : add 40mA, x18 : add 60mA

Add DC CHARACTERISTICS

- V

IN-CLK,

DIF-CLK,

CM-CLK

Add AC INPUT CHARACTERISTICS

Add INPUT DEFINITION

Draft Data

Oct. 2003

Nov. 2003

Remark

Advance

Preliminary

Rev. 0.2

Feb. 2004

Preliminary

Rev. 0.3

Feb. 2004

Preliminary

Rev. 1.0

Mar. 2004

Final

Rev. 1.1

Jan. 2004

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

-1-

Rev 1.1

Jan. 2005

K7D163674B

K7D161874B

Read Operation(Single and Double)

512Kx36 & 1Mx18 SRAM

During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is

read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of

K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal

array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by

burst order off the second rising and falling edge of K clock.

Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.

To avoid data contention,at least one NOP operations are required between the last read and the first write operation.

Write Operation(Late Write)

During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered

at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of

K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are

stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM

array.

Echo clock operation

Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation

only when K clock is in the stop mode.

Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture

data outputs outputs.

Bypass Read Operation

Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are

identical. For this case, data outputs are from the data in registers instead of SRAM array.

Programmable Impedance Output Driver

The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and V

, and

are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by

test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates

occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In

all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior

in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is

selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-

uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are

no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs

1024 non-read cycles.

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

-5-

Rev 1.1

Jan. 2005

K7D161874B-HC27 Related Products

	K7D161874B-HC27	K7D163674B-HC33	K7D161874B	K7D161874B-HC37	K7D161874B-HC30	K7D163674B-HC27	K7D163674B	K7D163674B-HC37	K7D161874B-HC33	K7D163674B-HC30
Description	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM	512Kx36 & 1Mx18 SRAM

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