K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
36Mb DDR SRAM Specification
153BGA with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.0 August 2006
K7D323674C
K7D321874C
Document Title
36M DDR SYNCHRONOUS SRAM
1Mx36 & 2Mx18 SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 1.0
History
Initial document.
Change AC Characteritics, Pin Capacitance, DC Characteristics
Change Samsung JEDEC Code in ID REGISTER DEFINITION
Correct Typo
Draft Data
Nov. 2005
Apr. 2006
Jun. 2006
Aug. 2006
Remark
Advance
Preliminary
Preliminary
Final
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Rev. 1.0 August 2006
K7D323674C
K7D321874C
FEATURES
1Mx36 or 2Mx18 Organizations.
1.8~2.5V V
DD
/1.5V ~1.8V
DDQ
.
HSTL Input and Outputs.
Single Differential HSTL Clock.
Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Registered Addresses, Burst Control and Data Inputs.
•
•
•
•
•
1Mx36 & 2Mx18 SRAM
• Registered Outputs.
• Double and Single Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleaved and Linear Burst mode support
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Ball Grid Array Package(14mmx22mm)
• No Output enable support.
GENERAL DESCRIPTION
The K7D323674C and K7D321874C are 37,748,736 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
1,048,576 words by 36 bits for K7D323674C and 2,097,152 words by 18 bits for K7D321874C, fabricated using Samsung's
advanced CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representative of data output access
time for all SDR and DDR operations.
The chip is operated with 1.8~2.5V power supply and is compatible with HSTL input and output. The package is 9x17(153) Ball Grid
Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Organization
1Mx36
Maximum Frequency
400MHz
375MHz
333MHz
400MHz
2Mx18
375MHz
333MHz
Part Number
K7D323674C-H(G)
1
C40
K7D323674C-H(G)
1
C37
K7D323674C-H(G)
1
C33
K7D321874C-H(G)
1
C40
K7D321874C-H(G)
1
C37
K7D321874C-H(G)
1
C33
Note 1. H(G) [Package type] : G-Pb Free, H-Pb
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Rev. 1.0 August 2006
K7D323674C
K7D321874C
FUNCTIONAL BLOCK DIAGRAM
SA[0:20]( or SA[0:21])
Address
Register
CE
20(or 21)
18(or 19)
(Burst Address)
Burst
Counter
(Burst Write
Address)
20(or 21)
18(or 19)
2:1
MUX
1Mx36 & 2Mx18 SRAM
Dec.
Data Out
K,K
Clock
Buffer
Memory Array
1Mx36
or
(2Mx18)
Data In
36(or18)x2
W/D
Array
36(or18)x2
Write Buffer
Comparator
B
1
B
3
Advance
Co
Control
SD/DD
Write
Address
Register
(2 stage)
CE
Synchronous
Select
&
R/W control
CE
R/W
LD
Internal
Clock
Generator
Data Output Strobe
Data Output Enable
State Machine
Strobe_out
36(or 18)x2
S/A Array
36(or 18)x2
2 : 1 MUX
B
2
Output
Buffer
Echo Clock
Output
Data In
Register
(2 stage)
36(or 18)
DQ
CQ,CQ
XDIN
PIN DESCRIPTION
Pin Name
K, K
SA
SA
0
, SA
1
DQ
CQ, CQ
B
1
B
2
B
3
LBO
ZQ
Pin Description
Differential Clocks
Synchronous Address Input
Synchronous Burst Address Input (SA
0
= LSB)
Synchronous Data I/O
Differential Output Echo Clocks
Load External Address
Burst R/W Enable
Single/Double Data Selection
Linear Burst Order
Output Driver Impedance Control Input
Pin Name
TCK
TMS
TDI
TDO
V
REF
V
DD
V
DDQ
V
SS
NC
Pin Description
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
Output Power Supply
GND
No Connection
-4-
Rev. 1.0 August 2006
K7D323674C
K7D321874C
PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
K7D323674C(1Mx36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
2
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
3
SA
SA
SA
SA
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
NC
*
V
DD
(4)
SA
TMS
4
SA
V
SS
SA
V
ss
(5)
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
LBO
V
DD
V
DD
V
SS
SA
V
SS
TDI
5
ZQ
B
1
SA
V
DD
V
REF
V
DD
K
K
V
DD
B
2
B
3
V
DD
V
REF
V
DD
(2)
SA
1
SA
0
TCK
6
SA
V
SS
SA
V
ss
(6)
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
1Mx36 & 2Mx18 SRAM
7
SA
SA
SA
SA
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
SA
V
DD
(3)
SA
NC
8
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
9
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
MODE(7)
V
DD
V
DD
V
SS
SA
V
SS
TDO
K7D321874C(2Mx18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
2
V
DDQ
DQ
V
DDQ
NC
V
DDQ
CQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
3
SA
SA
SA
SA
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
SA
V
DD
(4)
SA
TMS
4
SA
V
SS
SA
V
ss
(5)
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
LBO
V
DD
V
DD
V
SS
SA
V
SS
TDI
5
ZQ
B
1
SA
V
DD
V
REF
V
DD
K
K
V
DD
B
2
B
3
V
DD
V
REF
V
DD
(2)
SA
1
SA
0
TCK
6
SA
V
SS
SA
V
ss
(6)
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
MODE(7)
V
DD
V
DD
V
SS
SA
V
SS
TDO
7
SA
SA
SA
SA
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
SA
V
DD
(3)
SA
NC
8
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
CQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
9
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
(1) Variable address see "Variable address assignment table"
(2) Variable address see "Variable address assignment table"
(3) Variable address see "Variable address assignment table"
(4) Variable address see "Variable address assignment table"
(5) Variable address see "Variable address assignment table"
(6) Variable address see "Variable address assignment table"
(7) Internally NC
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Rev. 1.0 August 2006
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