K7B803625B
K7B801825B
256Kx36 & 512Kx18 Synchronous SRAM
8Mb Sync. Burst SRAM Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 6.0 April 2006
K7B803625B
K7B801825B
Document Title
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
Revision History
Rev. No.
0.0
0.1
0.2
1.0
History
Initial draft
Add x32 org part and industrial temperature part
1. change scan order(1) form 4T to 6T at 119BGA(x18)
1. Final spec release
2. Change I
SB2
form 50mA to 60mA
Change ordering information( remove 225MHz at SPB)
1. Delete 119BGA package
1. Remove x32 organization
2. Remove -85 speed bin
1. Add the lead-free package type
1. Add the overshoot timing
1. Change ordering information
Draft Date
May. 18 . 2001
Aug. 11. 2001
Aug. 28. 2001
Nov. 16. 2001
Remark
Preliminary
Preliminary
Preliminary
Final
2.0
2.1
3.0
April. 01. 2002
April. 04. 2003
Nov. 17. 2003
Final
Final
Final
4.0
5.0
6.0
May 31, 2005
Feb. 16. 2006
Apri. 03. 2006
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-2-
Rev. 6.0 April 2006
K7B803625B
K7B801825B
8Mb SB SRAM Ordering Information
Org.
512Kx18
256Kx36
VDD (V)
3.3
3.3
3.3
3.3
Speed (ns)
7.5
8.5
7.5
8.5
256Kx36 & 512Kx18 Synchronous SRAM
Access Time (ns)
6.5
7.5
6.5
7.5
Part Number
K7B801825B-P(Q)
1
C(I)
2
65
K7B801825B-Q
3
C(I)
2
75
K7B803625B-P(Q)
1
C(I)
2
65
K7B803625B-Q
3
C(I)
2
75
RoHS Avail.
√
•
√
•
Note 1. P(Q) [Package type] : P-Pb Free, Q-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
3. Support only Pb package Parts. For Pb-Free package, use faster frequency parts.
-3-
Rev. 6.0 April 2006
K7B803625B
K7B801825B
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A (Lead and Lead-Free package)
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7B803625B and K7B801825B are 9,437,184-bit Synchro-
nous Static Random Access Memory designed for high perfor-
mance second level cache of Pentium and Power PC based
System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B803625B and K7B801825B are fabricated using SAM-
SUNG′s high performance CMOS technology and is available
in a 100pin TQFP and Multiple power and ground pins are uti-
lized to minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -65
t
CYC
t
CD
t
OE
7.5
6.5
3.5
-75
8.5
7.5
3.5
-85 Unit
10
8.5
4.0
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A′
0
~A′
1
256Kx36 , 512Kx18
MEMORY
ARRAY
ADSP
A
0
~A
17
or A
0
~A
18
ADDRESS
REGISTER
A
2
~A
17
or A
2
~A
18
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DATA-IN
REGISTER
CONTROL
REGISTER
CONTROL
LOGIC
OUTPUT
BUFFER
DQa
0
~ DQd
7
or DQa0 ~ DQb7
DQPa ~ DQPd
DQPa,DQPb
-4-
Rev. 6.0 April 2006
K7B803625B
K7B801825B
PIN CONFIGURATION
(TOP VIEW)
WEd
WEb
WEc
256Kx36 & 512Kx18 Synchronous SRAM
ADSC
ADSP
WEa
A
6
ADV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
V
SS
A
5
A
4
A
3
A
2
A
1
A
0
A
17
A
10
A
12
A
13
A
14
A
15
LBO
N.C.
N.C.
V
DD
N.C.
PIN
SYMBOL
A
0
- A
17
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,41,65,91
17,40,67,90
14,16,38,39,42,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
32,33,34,35,36,37,43
44,45,46,47,48,49,50
81,82,99,100
83
ADV
Burst Address Advance
Address Status Processor 84
ADSP
Address Status Controller 85
ADSC
89
Clock
CLK
98
Chip Select
CS
1
97
Chip Select
CS
2
92
Chip Select
CS
2
93,94,95,96
WEx(x=a,b,c,d) Byte Write Inputs
86
Output Enable
OE
88
Global Write Enable
GW
87
Byte Write Enable
BW
64
Power Down Input
ZZ
31
Burst Mode Control
LBO
Output Power Supply
(2.5V or 3.3V)
Output Ground
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
2. The pin 42 is reserved for address bit for the 16Mb .
A
16
A
11
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
81
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7B803625B(256Kx36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
-5-
Rev. 6.0 April 2006
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