K7M163635B
K7M161835B
512Kx36 & 1Mx18 Flow-Through NtRAM
TM
18Mb NtRAM
TM
Specification
100TQFP/165FBGA with Pb/Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 3.0 April 2006
K7M163635B
K7M161835B
Document Title
512Kx36 & 1Mx18 Flow-Through NtRAM
TM
512Kx36 & 1Mx18-Bit Flow Through NtRAM
TM
Revision History
Rev. No.
0.0
0.1
0.2
History
1. Initial document.
1. Update the DC current spec(I
CC
, I
SB
)
1. Change the ISB,ISB1,ISB2
- ISB ; from 120mA to 170mA
- ISB1 ; from 80mA to 150mA
- ISB2 ; from 80mA to 130mA
1. Remove the 1.8V Vdd voltage level
1. Remove the -75 speed bin
1. Finalize the datasheet
1. Add the overshoot timing
1. Change ordering information
Draft Date
Mar. 23. 2004
May. 21. 2004
Sep. 21. 2004
Remark
Advance
Preliminary
Preliminary
0.3
0.4
1.0
2.0
3.0
Oct. 18. 2004
Jan. 04. 2004
July 18. 2005
Feb. 16. 2006
Apr. 04. 2006
Preliminary
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-2-
Rev. 3.0 April 2006
K7M163635B
K7M161835B
512Kx36 & 1Mx18 Flow-Through NtRAM
TM
18Mb NtRAM (Flow Through) Ordering Informa
tion
Org.
1Mx18
512Kx36
VDD (V)
3.3/2.5
3.3/2.5
Speed (ns)
7.5
7.5
Access Time (ns)
6.5
6.5
Part Number
K7M161835B-P(Q)
1
C(I)
2
65
K7M163635B-P(Q)
1
C(I)
2
65
RoHS Avail.
√
√
Note 1. P(Q) [Package type] : P-Pb Free, Q-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
-3-
Rev. 3.0 April 2006
K7M163635B
K7M161835B
512Kx36 & 1Mx18 Flow-Through NtRAM
TM
512Kx36 & 1Mx18-Bit Flow Through NtRAM
TM
FEATURES
• V
DD
= 2.5 or 3.3V +/- 5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A (Lead and Lead free package)
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7M163635B and K7M161835B are 18,874,368-bits Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M163635B and K7M161835B are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
FAST ACCESS TIMES
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Sym.
t
CYC
t
CD
t
OE
-65
7.5
6.5
3.5
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
LBO
ADDRESS
REGISTER
A
2
~A
18
or A
2
~A
19
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
512Kx36, 1Mx18
MEMORY
ARRAY
A [0:18]or
A [0:19]
CLK
CKE
K
WRITE
ADDRESS
REGISTER
K
DATA-IN
REGISTER
CONTROL
LOGIC
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
CONTROL
REGISTER
CONTROL
LOGIC
BUFFER
36 or 18
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
-4-
Rev. 3.0 April 2006
K7M163635B
K7M161835B
PIN CONFIGURATION
(TOP VIEW)
BWd
512Kx36 & 1Mx18 Flow-Through NtRAM
TM
BWb
BWa
BWc
CKE
ADV
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
A
18
A
6
A
17
83
OE
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
V
SS
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
12
A
13
A
14
A
15
LBO
V
DD
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
or NC
V
DDQ
V
SSQ
PIN NAME
TQFP PIN NO.
32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,84,99,100
ADV
Address Advance/Load 85
WE
Read/Write Control Input 88
89
Clock
CLK
87
Clock Enable
CKE
98
Chip Select
CS
1
97
Chip Select
CS
2
92
Chip Select
CS
2
93,94,95,96
BWx(x=a,b,c,d) Byte Write Inputs
86
Output Enable
OE
64
Power Sleep Mode
ZZ
31
Burst Mode Control
LBO
Power Supply(+3.3V) 15,16,41,65,91
14,17,40,66,67,90
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
38,39,42,43
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
A
11
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
5,10,21,26,55,60,71,76
Output Ground
Notes :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
A
16
50
NC/DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
Vss
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
NC/DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7M163635B(512Kx36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
SS
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
-5-
Rev. 3.0 April 2006
Embedded System
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