Enhanced
Features
s
Memory Systems Inc.
DM512K64DTE/DM512K72DTE
Multibank
Burst EDO EDRAM
512Kb x 64/512Kb x 72 Enhanced DRAM DIMM
Product Specification
8Kbytes SRAM Cache Memory for 12ns Random Reads Within
Four Active Pages (Multibank Cache)
s
Fast 4Mbyte DRAM Array for 30ns Access to Any New Page
s
Write Posting Registers for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
s
2Kbyte Wide DRAM to SRAM Bus for 113.8 Gigabytes/Second
Cache Fill Rate
s
On-chip Cache Hit/Miss Comparators Automatically Maintain
Cache Coherency on Writes
s
Hidden Precharge & Refresh Cycles
s
Extended 64ms Refresh Period for Low Standby Power
s
CMOS/TTL Compatible I/O and +5 Volt Power Supply
s
Linear or Interleaved Burst Mode Configurable Without Mode
Register Load Cycles
s
Fast Page to Page Move or Read-Modify-Write Cycles
s
Output Latch Enable Allows Extended Data Output (EDO) for
Faster System Operation
Description
The Enhanced Memory Systems 4MB enhanced DRAM
(EDRAM)DIMM module provides a single memory module solution
for the main memory or local memory of fast 64-bit PCs,
workstations, servers, and other high performance systems. Due to its
fast non-interleave architecture, the EDRAM DIMM module supports
zero-wait-state burst read or write operation to 100MHz. The EDRAM
outperforms conventional SRAM plus DRAM or synchronous DRAM
memory systems by minimizing wait states on initial reads (hit or
miss) and eliminating writeback delays.
Each 4Mbyte DIMM module has 8Kbytes of SRAM cache
organized as four 256 x 72 row registers with 12ns initial access
time. On a cache miss, the fast DRAM array reloads an entire 2Kbyte
row register over a 2Kbyte-wide
bus in just 18ns for an effective
cache fill rate of 113.8
Gbytes/second. During write
cycles, dual write posting registers
allow the initial writes to be posted
as early as 5ns after column
address is available. EDRAM
supports direct non-interleave
page writes at greater than 83MHz.
An on-chip hit/miss comparator
automatically maintains cache
coherency during writes.
The 4Mbyte DIMM module
implements the following new features which can be implemented on
new designs:
s
An optional synchronous burst mode for up to 100MHz burst
transfers.
s
Concurrent random page write and cache reads from four cache
pages allows fast page-to-page move or read-modify-write cycles.
s
A controllable output latch provides an extended data output
(EDO) mode.
Architecture
The DM512K72 achieves its 512Kb x 72 density by mounting 9
512Kx8 EDRAMs, packaged in low profile 44-pin TSOP-II packages
on one side of the multi-layer substrate. Three high drive series
terminated buffer chips buffer address and control lines. Twelve
surface mount capacitors are used to decouple the power supply bus.
The DM512K64 contains 8 512Kx8 EDRAMs. The parity data
component is not populated.
The EDRAM memory module architecture is very similar to two
standard 2MB DRAM SIMM modules configured in a 64-bit wide,
non-interleave configuration. The
EDRAM module adds an integrated
cache and cache control logic which
allow the cache to operate much like a
page mode or static column DRAM.
The EDRAM’s SRAM cache is
integrated into the DRAM array as tightly
coupled row registers. Memory reads
QLE
always occur from the 256 x 72 cache
/G
row register associated with a 1MB
I/O
Control
segment of DRAM. When the on-chip
DQ
0-71
and
comparator detects a page hit, only the
Data
Latches
SRAM is accessed and data is available
/S
in 12ns from column address. When a
/WE
page miss is detected, the entire new
DRAM row is loaded into cache and data
is available at the output within 30ns
from row enable. Subsequent reads
V
C
1-12
within a page (burst reads or random
V
reads) will continue at 12ns cycle time.
PD
Since reads occur from the SRAM cache,
CC
SS
Functional Diagram
/CAL
0-8
BE
BM
0-2
Column
Address
Latch and
Burst Control
A
0 -7
Column Decoder
4 - 256 X 72 Cache Pages
(Row Registers)
4-Bit
Comparators
Sense Amps
& Column Write Select
A
0
- A
10
4 - Last Row
Read Address
Latches
Row Decoder
Row
Address
Latch
Memory
Array
(4 Mbyte + Parity)
/F
W/R
/RE
Row Adress
and
Refresh
Control
A
0
- A
9
Refresh
Counter
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.
1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2124-000
the DRAM precharge can occur simultaneously without degrading
performance. The on-chip refresh counter with independent
refresh bus allows the EDRAM to be refreshed during cache reads.
Memory writes can be posted as early as 6.5ns after row
enable and are directed to the DRAM array. During a write hit, the
on-chip address comparator activates a parallel write path to the
SRAM cache to maintain coherency. Memory writes do not affect
the contents of the cache row register except during write hits.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior system performance at less cost, power, and
area than systems implemented with complex synchronous SRAM
cache, cache controllers, and multilevel data busses.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select column address bits A
8
and A
9
. The contents of these cache
row registers is always equal to the last row that was read from
each of the four internal DRAM banks (as modified by any write hit
data).
Row And Column Addressing
Like common DRAMs, the EDRAM requires the address to be
The EDRAM is designed to provide optimum memory
multiplexed into row and column addresses. Unlike other
performance with high speed microprocessors. As a result, it is
memories, the DM512K72 allows four read pages (DRAM pages
possible to perform simultaneous operations to the DRAM and
duplicated in SRAM cache) and one write page to be active at the
SRAM cache sections of the EDRAM. This feature allows the EDRAM same time. To allow any of the four active cache pages to be
to hide precharge and refresh operation during reads and
accessed quickly, the row address bits A
8-9
(DRAM bank selects)
maximize hit rate by maintaining page cache contents during write are also duplicated in the column address bits A
8-9
. This allows any
operations even if data is written to another memory page. These
cache bank to be selected by simply changing the column address.
capabilities, in conjunction with the faster basic DRAM and cache
The write bank address is specified by row address A
8-9
, and writes
speeds of the EDRAM, minimize processor wait states.
are inhibited when a different column bank select is enabled.
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F high. The EDRAM will compare the new row address to the
last row read address latch for the bank specified by row address
bits A
8-9
(LRR: a 9-bit row address latch for each internal DRAM
Functional Description
Four Bank Cache Architecture
Bank 3
Bank 2
Bank 1
Bank 0
Row Address Latch
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
CA , CA Column Address Latch
8
9
CA
0-7
1M Array
1M Array
1M Array
1M Array
D
0-71
A
0-10
Data-In
Latch
256 x 72
Cache
Bank 0
CA
0-7
256 x 72
Cache
Bank 1
256 x 72
Cache
Bank 2
256 x 72
Cache
Bank 3
(0,0)
CA
8
, CA
9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL
QLE
Data-Out
Latch
G
S
Q
0-71
3-32
row address matches the LRR, the EDRAM will write data to both the
DRAM page in the specified bank and its corresponding SRAM cache
simultaneously to maintain coherency. The write address and data
are posted to the DRAM as soon as the column address is latched by
bringing /CAL low and the write data is latched by bringing /WE low.
The write address and data can be latched very quickly after the fall
of /RE (t
RAH
+ t
ASC
for the column address and t
DS
for the data).
During a write burst or any page write sequence, the second write
data can be posted at time t
RSW
after /RE. Subsequent writes within
the page can occur with write cycle time t
PC
. With /G enabled and /WE
disabled, cache read operations may be performed while /RE is
activated. This allows random read from any of the four cache pages
and random write, read-modify-write, or write-verify to the current
write page with 12ns cycle times. To perform internal memory-to-
memory transfers, /WE can be brought low while /G is low to latch
the read data into the write posting register. The read/write transfer
DRAM Read Miss
is complete when the new write column address is latched by bringing
A DRAM read request is initiated by clocking /RE with W/R low /CAL low concurrently with /WE. At the end of any write sequence
and /F high. The EDRAM will compare the new row address to the (after /CAL and /WE are brought high and t is satisfied), /RE can
RE
LRR address latch for the bank specified by row address bits A
8-9
be brought high to precharge the memory. Reads can be performed
(LRR: a 9-bit row address latch for each internal DRAM bank
from any of the cache pages concurrently with precharge by providing
which is reloaded on each /RE active read miss cycle). If the row
the desired column address and column bank select bits CA
8-9
to
address does not match the LRR, the requested data is not in SRAM the multiplex address inputs. During write sequences, a write
cache and a new row is fetched from the DRAM. The EDRAM will
operation is not performed unless both /CAL and /WE are low. As a
load the new row data into the SRAM cache and update the LRR
result, the /CAL input can be used as a byte write select in multi-chip
latch. The data at the specified column address is available at the
systems. If /CAL is not clocked on a write sequence, the memory will
output pins at the greater of times t
RAC
, t
AC
, and t
GQV
. /RE may be
perform an /RE only refresh to the selected row and data will
brought high after time t
RE
since the new row data is safely latched remain unmodified. Writes are inhibited for any write having a
into SRAM cache. This allows the EDRAM to precharge the DRAM
column address bank select different from the bank selected by the
array while data is accessed from SRAM cache. Additional locations row address.
within the currently active page may be accessed by providing new
DRAM Write Miss
column addresses to the multiplex address inputs. New data is
A DRAM write request is initiated by clocking /RE while W/R, /WE,
available at the output at time t
AC
after each column address change
and /F are high. The EDRAM will compare the new row address to the
in static column mode. During any read cycle, it is possible to
LRR address latch for the bank specified by row address A
8-9
(LRR:
operate in either static column mode with /CAL=high or page
a 9-bit row address latch for each internal DRAM bank which is
mode with /CAL clocked to latch the column address. In page
reloaded on each /RE active read miss cycle). If the row address
mode, data valid time is determined by either t
AC
and t
CQV
.
does not match the LRR, the EDRAM will write data only to the DRAM
DRAM Write Hit
page in the appropriate bank and the contents of the current cache is
A DRAM write request is initiated by clocking /RE while W/R,
not modified. The write address and data are posted to the DRAM as
/WE, and /F are high. The EDRAM will compare the new row
soon as the column address is latched by bringing /CAL low and the
address to the LRR address latch for the bank specified by row
write data is latched by bringing /WE low. The write address and data
address A
8-9
(LRR: a 9-bit row address latch for each internal DRAM can be latched very quickly after the fall of /RE (t
RAH
+ t
ASC
for the
column address and t
DS
for the data). During a write burst or any
bank which is reloaded on each /RE active read miss cycle). If the
bank which is reloaded on each /RE active read miss cycle). If the
row address matches the LRR, the requested data is already in the
SRAM cache and no DRAM memory reference is initiated. The data
specified by the row and column address is available at the output
pins at the greater of times t
AC
or t
GQV
. Since no DRAM activity is
initiated, /RE can be brought high after time t
RE1
, and a shorter
precharge time, t
RP1
, is required. Additional locations within the
currently active page may be accessed concurrently with precharge
by providing new column addresses to the multiplex address
inputs. New data is available at the output at time t
AC
after each
column address change in static column mode. During any read
cycle, it is possible to operate in either static column mode with
/CAL=high or page mode with /CAL clocked to latch the column
address. In page mode, data valid time is determined by either t
AC
and t
CQV
.
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
/S
L
L
L
L
X
H
H
/RE
↓
↓
↓
↓
↓
H
L
W/R
L
L
H
H
X
X
X
/F
H
H
H
H
L
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
Standby Current
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
3-33
page write sequence, the second write data can be posted at time
t
RSW
after /RE. Subsequent writes within the page can occur with
write cycle time t
PC
. With /G enabled and /WE disabled, cache read
operations may be performed while /RE is activated. This allows
random read accesses from any of the four cache pages and random
writes to the current write page with 12ns cycle times. To perform
internal memory-to-memory transfers, /WE can be brought low while
/G is low to latch the read data into the write posting register. The
read/ write transfer is complete when the new write column address
is latched by bringing /CAL low concurrently with /WE. At the end of
any write sequence (after /CAL and /WE are brought high and t
RE
is
satisfied), /RE can be brought high to precharge the memory. Reads
can be performed from any of the cache pages concurrently with
precharge by providing the desired column address and column
bank select bits CA
8-9
to the multiplex address inputs. During write
sequences, a write operation is not performed unless both /CAL and
/WE are low. As a result, /CAL can be used as a byte write select in
multi-chip systems. If /CAL is not clocked on a write sequence, the
memory will perform an /RE only refresh to the selected row and
data will remain unmodified. Writes are inhibited for any write
having a column address bank select different from the bank
selected by the row address.
/RE Inactive Operation
Data may be read from any of the four SRAM cache pages
without clocking /RE. This capability allows the EDRAM to perform
cache read operations during precharge and refresh cycles to
minimize wait states. It is only necessary to select /S and /G and
provide the appropriate column address to read data as shown in the
table below. In this mode of operation, the cache reads may occur
from any of the four pages as specified by column bank select bits
CA
8-9
. To perform a cache read in static column mode, /CAL is held
high, and the cache contents at the specified column address will be
valid at time t
AC
after address is stable. To perform a cache read in
page mode, /CAL is clocked to latch the column address.
This option allows the external logic to perform fast hit/miss
comparison so that the time required for row/column multiplexing
is avoided.
Function
Cache Read (Static Column)
Cache Read (Page Mode)
QLE
L
¤
H
/CAL
X
H
¤
Output Transparent
Comments
Output Latched When QLE=H (Static Column EDO)
Output Latched When /CAL=H (Page Mode EDO)
Burst Mode Operation
Burst mode provides a convenient method for high speed
sequential reading or writing of data. To enter burst mode, the
starting address, a burst enable signal (BE) and burst mode
information (BM
0-2
) as shown in the following table must be
provided. Random accesses using external addresses or new burst
sequences may be performed after a burst sequence is terminated.
To start a burst cycle, BE must be brought high prior to the
falling edge of /CAL. At the falling edge of /CAL, the EDRAM latches
the starting address and the states of the burst mode pins (BM
0-2
)
which define the type and wrap length of the burst. Once a burst
sequence has been started, the internal address counter increments
BM
2,1,0
0-0-0
0-0-1
Burst Type
Linear
Linear
Wrap Length
2
4
Address Sequence
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
(B)(S),(B)(S+1),…
(B)(255),(B)(0),…
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
(B)(S),(B)(S+1),…
(B)(255),(B+1)(0),…
0-1-0
Linear
8
0-1-1
1-0-0
1-0-1
Linear
Interleaved
(Scrambled)
Interleaved
(Scrambled)
Full Page
2
4
/S
L
L
/G
L
L
/CAL
H
¤
A
0-7
Col Adr
Col Adr
1-1-0
Interleaved
(Scrambled)
8
EDO Mode and Output Latch Enable Operation
The QLE and /CAL inputs can be used to create extended data
output (EDO) mode timings in either static column or page modes.
The DM512K72 EDRAM has an output latch enable (QLE) that can
be used to extend the data output valid time. The output latch
enable operates as shown in the following table.
When QLE is low, the latch is transparent and the EDRAM
operates identically to the standard EDRAMs. When /CAL is high
during a static column mode read, the QLE input can be used to
latch the output to extend the data output valid time. QLE can be
held high during page mode reads, In this case, the data outputs
are latched while /CAL is high and open when /CAL is not high.
When output data is latched and /S goes high, data does not go
Hi-Z until /G is disabled or either QLE or /CAL goes low to unlatch
data.
1-1-1
NOTES:
Linear
All Pages
a) B=Bank Address, S=Starting Column Address;
b) For BM
2,1,0
=111, wrap length is 1,024 8-bit words with 256 8-bit words
for each of the four cache blocks. During read or write sequences, the
address count will switch from bank to bank after column address 256.
Write operations, however, will only occur when the internally generated
bank address A
8
and A
9
matches the row address A
8
and A
9
that were
loaded when /RE went low.
3-34
Following these start-up cycles, two read cycles to different row
addresses must be performed for each of the four internal banks of
DRAM to initialize the internal cache logic. Row address bits A
8
and
A
9
define the four internal DRAM banks.
Unallowed Mode
Read, write, or /RE only refresh operations must not be performed
to unselected memory banks by clocking /RE when /S is high.
Reduced Pin Count Operation
Although it is desirable to use all EDRAM control pins to optimize
system performance, the interface to the EDRAM may be simplified to
reduce the number of control lines by either tying pins to ground or
tying one or more control inputs together. The /S input can be tied to
ground if low power standby mode is not required. The QLE input can
be tied low if output latching is not required, or tied high if “extended
Write-Per-Bit Operation
data out” (hyper page mode) is required. BE can be tied low if burst
The DM512K72 DIMM provides a write-per-bit capability to
operation is not desired. The W/R and /G inputs can be tied together
selectively modify individual parity bits (DQ
8, 17, 26, 35, 44, 53, 62, 71
)for
if reads are not required during a write cycle. The simplified control
byte write operations. The parity device (DM2233) is selected via
/CAL
8
. Byte write selection to non-parity bits is accomplished via CAL
0-7
.
interface still allows the fast page read/write cycle times, fast random
The bits to be written are determined by a bit mask data word which
read/write times, and hidden precharge functions available with the
is placed on the parity I/O data pins prior to clocking /RE. The logic
EDRAM.
one bits in the mask data select the bits to be written. As soon as the
mask is latched by /RE, the mask data is removed and write data can
Pin Descriptions
be placed on the databus. The mask is only specified on the /RE
/RE — Row Enable
transition. During page mode write operations, the same mask is used
This input is used to initiate DRAM read and write operations
and latch a row address. It is not necessary to clock /RE to read
for all write operations.
data from the EDRAM SRAM row registers. On read operations, /RE
ECC Operation
can be brought high as soon as data is loaded into cache to allow
The DM512K72DTE-xxN supports error correction coding
early precharge.
(ECC) by replacing the parity chip with a normal DM2223 device.
/CAL
0-8
— Column Address Latch
This version does not support write-per-bit.
These inputs are used to latch the column address and in
Internal Refresh
combination with /WE to trigger write operations. When /CAL is high,
If /F is active (low) on the assertion of /RE, an internal refresh
the column address latch is transparent. When /CAL is low, the
cycle is executed. This cycle refreshes the row address supplied by
column address latch contains the address present at the time /CAL
an internal refresh counter. This counter is incremented at the end
went low. Individual /CAL inputs are provided for each byte of each
of the cycle in preparation for the next /F refresh cycle. At least
bank of EDRAM to allow byte write capability.
1,024 /F cycles must be executed every 64ms. /F refresh cycles can
W/R — Write/Read
be hidden because cache memory can be read under column
This input along with /F input specifies the type of DRAM
address control throughout the entire /F cycle. /F cycles are the
operation initiated on the low going edge of /RE. When /F is high,
only active cycles during which /S can be disabled. /RE must be
W/R specifies either a write (logic high) or read operation (logic
held high for 300ns prior to initialization.
low).
/RE Only Refresh Operation
/F — Refresh
Although /F refresh using the internal refresh counter is the
This input will initiate a DRAM refresh operation using the
recommended method of EDRAM refresh, an /RE only refresh may
internal refresh counter as an address source when it is low on the
be performed using an externally supplied row address. /RE refresh
low going edge of /RE.
is performed by executing a
write cycle
(W/R and /F are high)
/WE — Write Enable
where /CAL is not clocked. This is necessary so that the current
This input controls the latching of write data on the input data
cache contents and LRR are not modified by the refresh operation.
pins. A write operation is initiated when both /CAL for the specified
All combinations of addresses A
0-9
must be sequenced every 64ms
refresh period. A
10
does not need to be cycled. Read refresh cycles byte and /WE are low.
are not allowed because a DRAM refresh cycle does not occur when
/BE — Burst Enable
a read refresh address matches the LRR address latch.
This input is used to enable and disable the burst mode
function.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
/BM — Burst Mode
0-2
mode, the internal DRAM circuitry is powered down to reduce
These input pins define the burst type and address wrap
standby current.
around length during burst reads and write transfers.
Initialization Cycles
/G — Output Enable
A minimum of eight /RE active initialization cycles (read, write,
This input controls the gating of read data to the output data
or refresh) are required before normal operation is guaranteed.
pins during read operations.
3-35
with each low to high transition of /CAL. Burst mode is terminated
immediately when either BE goes low or /S goes high (/S must not
go high while /RE is low). Burst mode must be terminated before a
subsequent burst sequence can be initiated. Furthermore, the state
of the address counter is indeterminate following a burst
termination and must be reloaded for a subsequent burst operation.
Burst reads may be performed from any of the four cache pages and
may occur with /RE either active or inactive. As with all writes,
however, burst writes may only be performed to the currently active
write page (defined by the row address) while /RE is active.
Burst mode may be used with or without output latch enable
operation. If burst mode is not used, BE and BM
0-2
may be tied to
ground to disable the burst function.
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