The DPS2MS8MU is a 2M X 8 high-density, low-power static RAM module comprised of four 512K X 8 monolithic SRAM’ an advanced
s,
high-speed CMOS decoder and decoupling capacitors surface mounted on an epoxy laminate substrate.
The DPS2MS8MU operates from a single +5V supply and all input and output pins are completely TTL-compatible. The low standby power of the
DPS2MS8MU makes it ideal for battery-backed applications.
FEATURES:
•
2 Meg by 8 Bit Configuration
•
Access Times: 70, 85, 100, 120, 150ns
•
Low Power Dissipation:
•
2.2 mW (max.) Standby
360 mW (max.) Operating
PIN-OUT DIAGRAM
•
2-Volt Data Retention
•
Fully Static Operation - No Clock or Refresh Required
•
All inputs and Outputs are TTL-Compatible
•
36-PIN Plastic SIP Package
PIN NAMES
A0 - A20
I/O0 - I/O7
CE
WE
OE
V
DD
V
SS
Address Inputs
Data In/Out
Chip Enable
Write Enable
Output Enable
Power (+5V)
Ground
FUNCTIONAL BLOCK DIAGRAM
30A082-02
REV. A
This document contains information on a product under consideration for development at Dense-Pac Microsystems, Inc.
Dense-Pac reserves the right to change or discontinue information on this product without prior notice.
1
DPS2MS8MU
ADVANCED INFORMATION
Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE
1
Symbol
V
DD
V
IH
V
IL
T
A
Characteristic
Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Operating Temperature
Min. Typ.
4.5
5.0
2.2
-0.5
2
0
+25
Max.
5.5
V
DD
+0.3
0.8
+70
Unit
V
V
V
°
C
Mode
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
TRUTH TABLE
CE
H
L
L
L
WE
X
H
H
L
L = LOW
OE
X
H
L
X
I/O Pin
HIGH-Z
HIGH-Z
D
OUT
D
IN
Supply
Current
Standby
Active
Active
Active
X = Don’ Care
t
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
HIGH Voltage
V
OH
LOW Voltage
V
OL
Conditions
I
OH
= -1.0mA
I
OL
= 2.1mA
Min. Max. Unit
2.4
-
V
0.4
V
CAPACITANCE
4
:
T
A
= 25°C, F = 1.0MHz
ABSOLUTE MAXIMUM RATINGS
3
Symbol
T
STC
T
BIAS
V
DD
V
I/O
Parameter
Storage Temperature
Temperature Under Bias
Supply Voltage
1
Input/Output Voltage
1
Max.
-40 to +125
-10 to +85
-0.5 to + 7.0
-0.5 to V
DD
+0.5
Unit
°
C
°
C
V
V
Symbol
C
ADR
C
CE
C
WE
C
OE
C
I/O
Parameter
Address Input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Max.
45
20
45
45
50
Unit
Condition
pF
V
IN
= 0V
DC OPERATING CHARACTERISTICS:
Over operating ranges
Symbol
I
IN
I
OUT
I
CC1
I
CC2
I
SB1
I
SB2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Active Supply Current
Operating
Supply Current
Full Standby Supply Current
(CMOS)
Standby Current (TTL)
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
, CE or OE = V
IH
, or WE = V
IL
CE = V
IL
, V
IN
= V
IH
or V
IL
, I
OUT
=01mA
Cycle = min., Duty = 100%, I
OUT
= 0mA
V
IN
≥
V
DD
-0.2V or V
IN
≤
V
SS
+0.2V, CE
≥
V
DD
-0.2V
CE = V
IH
, V
IN
= V
IH
or V
IN
I
OUT
= 2.1mA
I
OUT
= -1.0mA
COMMERCIAL
Min.
Max.
Unit
µA
µA
mA
mA
µA
mA
V
V
-5
-5
+5
+5
20
65
400
12
0.4
2.4
DATA RETENTION CHARACTERISTICS
Symbol
V
DR
I
CCDR2
I
CCDR3
t
CDR
t
R
Parameter
Data Retention Voltage
Data Retention Supply Current
Data Retention Supply Current
Chip Disable to Data Retention Time
Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V
V
DR
= 2.0V
V
DR
= 3.0V
t
RC
= Read Cycle Timing
Min.
2.0
Max.
5.5
180
200
Unit
V
µA
µA
ns
ms
0
5
2
30A082-02
REV. A
Dense-Pac Microsystems, Inc.
ADVANCED INFORMATION
DPS2MS8MU
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output Timing Reference Levels
* Transition measured between 0.8V and 2.2V.
Output Load
0V to 3.0V
5ns *
1.5V
Load
1
2
C
L
100pF
5pF
Parameters Measured
except t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
WLZ
t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, and t
WLZ
DATA RETENTION WAVEFORM
V
DD
4.5V
Figure 1.
Output Load
** Including Probe and Jig Capacitance.
+5V
1.8KΩ
2.2V
V
DR
CE
V
SS
D
OUT
C
L
**
990Ω
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
t
RC
t
AA
t
CO
t
OV
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
Parameter
Read Cycle Time
Address Access Time
Chip Enable to Output Valid
Output Enable to Output Valid
Output Hold from Address Change
Chip Enable to Output in LOW-Z
4, 6
Output Enable to Output in LOW-Z
4, 6
Chip Enable to Output in HIGH-Z
4, 6
Output Enable to Output in HIGH-Z
4, 6
70ns
Min.
Max.
85ns
Min.
Max.
100ns
Min.
Max.
120ns
Min.
Max.
150ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
70
70
40
10
10
5
40
25
85
85
85
40
10
10
5
45
30
100
100
100
45
10
10
5
45
30
120
120
120
50
10
10
5
50
35
150
150
150
60
10
10
5
60
45
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE:
Over operating ranges
7
No. Symbol
10
11
12
13
14
15
16
17
18
19
t
WC
t
AW
t
CW
t
DW
t
DH
t
WP
t
AS
t
AH
t
WHZ
t
WLZ
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Data to Write Time Overlap
Data Hold Time from Write Time
Write Pulse Width
Address Set-up Time ***
Address Hold Time
Write Enable to Output in HIGH-Z
4, 6
Write Enable to Output in LOW-Z
4, 6
70ns
Min.
Max.
85ns
Min.
Max.
100ns
Min.
Max.
120ns
Min.
Max.
150ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
65
65
30
0
50
0
5
25
5
85
80
80
35
0
55
0
5
30
5
100
90
90
35
0
65
0
5
30
5
120
105
105
40
0
75
0
5
35
5
150
115
115
50
0
85
0
5
40
5
*** Valid for both Read and Write Cycles.
† Available in commercial only.
30A082-02
REV. A
3
DPS2MS8MU
ADVANCED INFORMATION
Dense-Pac Microsystems, Inc.
READ CYCLE 1:
Address Controlled. WE is HIGH. CE and OE are LOW.
ADDRESS
DATA I/O
READ CYCLE 2:
CE Controlled. WE is HIGH.
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1:
WE Controlled. OE is LOW.
ADDRESS
CE
WE
DATA I/O
4
30A082-02
REV. A
Dense-Pac Microsystems, Inc.
ADVANCED INFORMATION
DPS2MS8MU
NOTES:
1.
All voltages are with respect to V
SS
.
2.
-2.0V min. for pulse width less than 20ns (V
IL
min.= -0.5V at DC level).
3.
Stresses greater than those under
ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
4.
This parameter is guaranteed and not 100% tested.
5.
Transition is measured at the point of ±500mV from steady state voltage.
6.
When OE and CE are LOW and WE is HIGH, I/O pins are in the output state, and input signals of opposite phase to the outputs must not be applied.
7.
The outputs are in a high impedance state when WE is LOW.
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