• All inputs except data & DM are sampled at the positive going edge of the
system clock (CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM for write masking only.
• Auto refresh duty cycle.
- 7.8us
• Clock stop capability
• 2/CS, 2CKE
Operating Frequency
DDR400
Speed @CL3
1)
NOTE :
1) CAS Latency
200MHz
Address configuration
Organization
64Mx32
64Mx32
/CS
CS0
CS1
CKE
CKE0
CKE1
Bank
BA0,BA1
BA0,BA1
Row
A0 - A13
A0 - A13
Column
A0 - A9
A0 - A9
- DM is internally loaded to match DQ and DQS identically.
-3-
KA100O015E-BJTT
datasheet
Rev. 1.0
MCP Memory
2. GENERAL DESCRIPTION
The KA100O015E is a Multi Chip Package Memory which combines 4G bit NAND Flash Memory and 4G bit DDP synchronous high data rate Dynamic
RAM.
NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 420μs(TBD) on
the (2K+64)Word page and an erase operation can be performed in typical 3ms(TBD) on a (128K+4K)Word block. Data in the data register can be read
out at 42ns cycle time per Word. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller
automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-
intensive systems can take advantage of the device′s extended reliability of TBD program/erase cycles by providing ECC(Error Correcting Code) with real
time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
In 4G bit DDP Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, pro-
grammable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory sys-
tem applications.
The KA100O015E is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This
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