EURO
QUARTZ
11.4 x 9.6 x 4.7mm SMD
Frequency range 60MHz to 240MHz
LVPECL Output
Supply Voltage 3.3 VDC
Phase jitter 0.2ps typical
Pull range from ±30ppm to ±150ppm
DESCRIPTION
GPA64 VCXOs are packaged in a 6 pad 11.4 x 9.6mm SMD package.
Typical phase jitter for GPA series VCXOs is 0.2 ps. Output is LVPECL.
Applications include phase lock loop, SONET/ATM, set-top boxes,
MPEG , audio/video modulation, video game consoles and HDTV.
GPA64 PECL VCXO
60.0MHz to 240.0MHz
OUTLINE & DIMENSIONS
SPECIFICATION
Frequency Range:
Supply Voltage:
Output Logic:
RMS Period Jitter
60.0MHz ~ 120MHz:
120MHz ~ 240MHz:
Peak to Peak Jitter
60.0MHz ~ 120MHz:
120MHz ~ 240MHz:
Phase Jitter:
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
60.0MHz to 240.0MHz
3.3 VDC ±5%
LVPECL
2.5ps typical
4.7ps typical
17.5ps typical
24.5ps typical
0.2ps typical
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
Vdd-1.025V minimum
Vdd-0.880V maximum
Vdd-1.810V minimum
Vdd-1.620V maximum
(RL=50 to Vdd-2V)
From ±30ppm to ±150ppm
1.65 ±0.35 Volts
See table
50W into Vdd or Thevenin equiv.
0.5ns typ., 0.7ns max.
20% Vdd to 80% Vdd
50% ±5%
(Measured at Vdd-1.3V)
10ms maximum, 5ms typical
75mA maximum at 212.5MHz
80mA maximum at 622.08MHz
2kV maximum
-55° to +150°C
±2ppm per year maximum
See table
Fully compliant or non-compliant
Pulling Range:
Control Voltage Range:
Temperature Stability:
Output Load:
Rise/Fall Times:
Duty Cycle:
Start-up Time:
Current Consumption:
Static Discharge Protection:
Storage Temperature:
Ageing:
Enable/Disable:
RoHS Status:
FREQUENCY STABILITY
PART NUMBERING
Example:
Supply Voltage
3 = +3.3V
Series Designator
GPA64
RoHS Status
G = Compliant
Blank - Non-compliant
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
3GPA64GB-80N-60.000
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
ENABLE/DISABLE FUNCTION
Tristate Pad
Status
Not connected
Below 0.3Vdd
(Ref. to ground)
Above 0.7Vdd
(Ref. to ground)
Output Status
LVPECL and Complimentary LVPECL enabled
Both outputs are disabled (high impedance)
Both outputs are enabled
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
FPGA/CPLD
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