MICRF001
QwikRadio Receiver/Data Demodulator
Advance Information
General Description
The MICRF001 is a single chip OOK (ON-OFF Keyed) Receiver
IC for remote wireless applications, employing Micrel’s latest
QwikRadio
tm
technology. This device is a true “antenna-in, data-
out” monolithic device. All RF and IF tuning is accomplished
automatically within the IC, which eliminates manual tuning, and
reduces production costs. Receiver functions are completely
integrated. The result is a highly reliable yet extremely low cost
solution for high volume wireless applications. Because the
MICRF001 is a true single-chip radio receiver, it is extremely
easy to apply, minimizing design and production costs, and
improving time to market.
The MICRF001 uses a novel architecture that allows the
receiver to demodulate signals over a wide RF band, which
eliminates the need for manual tuning. This also significantly
relaxes the frequency accuracy and stability requirements of the
Transmitter, allowing the MICRF001 to be compatible with both
SAW-based and LC-based transmitters. The receiver sensitivity
and selectivity are sufficient to provide low bit error rates for
decode ranges over 100 meters, equaling the performance of
other more expensive solutions.
All tuning and alignment are accomplished on-chip by a low-
cost ceramic resonator or with an externally supplied clock
reference. Initial tolerance requirements on the ceramic
resonator or external clock is a modest ±0.5%. The MICRF001
performance is insensitive to data modulation duty cycle. The
MICRF001 may be used with such coding schemes as
Manchester or 33/66% PWM.
All post-detection (demodulator) data filtering is provided on the
MICRF001, so no external filters need to be designed. Any one
of four filter bandwidths may be selected externally by the user.
Bandwidths range from 0.6kHz to 4.8kHz in binary steps
tm
Features
•
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•
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Complete UHF receiver on a monolithic chip
Frequency range 300 to 440 MHz
Typical range over 100 meters with monopole
antenna
Data rates to 4.8kbps
Automatic tuning, no manual adjustment
No Filters or Inductors required
Very low RF re-radiation at the antenna
Direct CMOS logic interface to standard decoder and
microprocessor ICs
Extremely low external part count
Applications
•
•
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Keyless Entry
Security Systems
Remote Fan/Light Control
Garage Door Openers
Typical Operating Circuit
387 MHz, 1200 BAUD OOK RECEIVER
Micrel Inc. • 1849 Fortune Drive San Jose, Ca 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
MICRF001
QwikRadio
tm
Micrel
Ordering Information
Part Number
MICRF001BN
MICRF001BM
Pin Configuration (DIP and SOIC)
Temperature Range
-40°C to +85°C
-40°C to +85°C
Package
14-Pin DIP
14-Pin SOIC
Figure 1
Pin Description
Pin Number
1
2/3
Pin Name
SEL0
VSSRF
Pin Function
Programs desired Demodulator Filter Bandwidth. This pin in internally pulled-up to VDD. See Table 1.
This pin is the ground return for the RF section of the IC. The bypass capacitor connected from VDDRF to
VSSRF should have the shortest possible lead length. For best performance, connect VSSRF to VSSBB at
the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).
This is the receive RF input, internally ac-coupled. Connect this pin to the receive antenna. Input
impedance is high (FET gate) with approximately 2pF of shunt (parasitic) capacitance. For applications
located in high ambient noise environments, a fixed value band-pass network may be connected between
the ANT pin and VSSRF to provide additional receive selectivity and input overload protection. (See
“Application Note 22, MICRF001 Theory of Operation”.)
This pin is the positive supply input for the RF section of the IC. VDDBB and VDDRF should be connected
directly at the IC pins. Connect a low ESL, low ESR decoupling capacitor from this pin to VSSRF, as short
as possible.
This pin is the positive supply input for the baseband section of the IC. VDDBB and VDDRF should be
connected directly at the IC pins.
This capacitor extracts the (DC) average value from the demodulated waveform, which becomes the
reference for the internal data slicing comparator. Treat this as a low-pass RC filter with source impedance
described in Table 1 . (See
“Application Note 22, MICRF001 Theory of Operation”,
section 6.4). A
standard
±
20% X7R ceramic capacitor is generally sufficient.
Output data pin. CMOS level compatible.
This is the ground return for the baseband section of the IC. The bypass and output capacitors connected
to VSSBB should have the shortest possible lead lengths. For best performance, connect VSSRF to
VSSBB at the power supply only (i.e., keep VSSBB currents from flowing through VSSRF return path).
Integrating capacitor for on-chip receive AGC. The Decay/Attack time-constant (TC) ratio is nominally set
as 10:1. CAGC = 10(Attack Time Constant)
µF.
A standard
±
20% X7R ceramic capacitor is generally
sufficient.
Programs desired Demodulator Filter Bandwidth. This pin in internally pulled-up to VDD. See Table 1.
This is the timing reference for on-chip tuning and alignment. Either connect a ceramic resonator between
this pin and VSSBB, or drive the input with an AC coupled 0.5Vpp input clock. Use ceramic resonators
without integral capacitors. See
“Application Note 22, MICRF001 Theory of Operation”
for details on
frequency selection and accuracy.
This logic pin controls the operating mode of the MICRF001. When SWEN = HIGH, the MICRF001 is in
SWP mode. This is the normal (default) mode of the device. When SWEN = LOW, the device operates as
a conventional single-conversion superheterodyne receiver. (See
“Application Note 22, MICRF001 Theory
of Operation”
for details.) This pin is internally pulled-up to VDD.
4
ANT
5
VDDRF
6
7
VDDBB
CTH
8
9/10
DO
VSSBB
11
CAGC
12
13
SEL1
REFOSC
14
SWEN
June 1998
2
MICRF001
MICRF001
QwikRadio
tm
Micrel
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDDRF, VDDBB)...................................+7V
Voltage on any I/O Pin...........................VSS-0.3 to VDD+0.3
Junction Temperature.................................................+150°C
Storage Temperature Range......................-65°C to + 150°C
Lead Temperature (soldering, 10 seconds)..............+ 300°C
Operating Ratings
Supply Voltage (VDDRF, VDDBB)....................4.75V to 5.5V
Ambient Operating Temperature (TA)............-40°C to +85°C
Package Thermal Resistance
θja
(14 Pin DIP)..........90°C/W
This device is ESD sensitive: Meets Class 1 ESD test
requirements (Human Body Model, HBM), in accordance with
MIL-STD-883C, Method 3015. Do not operate or store near
strong electrostatic fields. Use appropriate ESD precautions.
Electrical Characteristics
Parameter
Power Supply
Operating Current
Operating Current
RF/IF Section
Receiver Sensitivity
IF Center Frequency
IF Bandwidth
Receive Data Rate
RF Input Range
Receive Modulation Duty-Cycle
Maximum Receiver Input
Spurious Reverse Isolation
AGC Attack / Decay ratio
Oscillator Turn-on Time
Demod Section
CTH Source Impedance
CTH Source Impedance Variation
Digital Section
REFOSC Input Impedance
Input Pullup Impedance
Output Current
Output High Voltage
Output Low Voltage
Output Tr, Tf
Note 1:
Unless otherwise stated, these specifications apply for Ta=-40°C to 85°C, 4.75<VDD<5.5V. All voltages are with respect to
Ground. CAGC = CTH = .047µF, VDDRF= VDDBB = VDD. REFOSC frequency = 2.442MHz.
Test Conditions
Ta= 25°C
Reference Oscillator powered down
Note 1, 3
Note 3
MIN
TYP
6.3
2
-95
2.25
1.0
MAX
UNITS
mA
mA
dBm
MHz
MHz
0.1
300
20
Rs = 50Ω
ANT pin, Rs = 50Ω Note 2
T(Attack) / T(Decay)
-20
30
0.1
0.1
SEL0=SEL1=VDD, See Table 1
-15
200k
SEL0, SEL1, SWEN
DO pin, Push-Pull
DO pin, Iout = 1µA
DO pin, Iout = 1µA
DO pin, Cload=15pF
0.9VDD
1000k
10
200k
4.8
440
80
kbps
MHz
%
dBm
µVrms
s
Ω
+15
%
Ω
Ω
µA
V
0.1VDD
10
V
µsec
Note 2:
Note 3:
Sensitivity is defined as the average signal level measured at the input necessary to achieve 10e-2 Bit Error Rate (BER). The
input signal is defined as a return-to-zero (RZ) waveform with 50% average duty cycle at a data rate of 2400bps. The RF input
is assumed to be matched into 50Ω.
Spurious reverse isolation represents the spurious components which appear on the RF input (ANT) pin measured into 50Ω
with an input RF matching network.
Sensitivity, a commonly specified Receiver parameter, provides an indication of the Receiver’s input referred noise, generally
input thermal noise. However, it is possible for a more sensitive receiver to exhibit range performance no better than that of a
less sensitive receiver, if the “ether” noise is appreciably higher than the thermal noise. “Ether” noise refers to other interfering
“noise” sources, such as FM radio stations, pagers, etc.
A better indicator of receiver range performance is usually given by its Selectivity, often stated as Intermediate Frequency (IF)
or Radio Frequency (RF) bandwidth, depending on receiver topology. Selectivity is a measure of the rejection by the receiver
of “ether” noise. More selective receivers will almost invariably provide better range. Only when the receiver selectivity is so
high that most of the noise on the receiver input is actually thermal will the receiver demonstrate sensitivity-limited
performance.
June 1998
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MICRF001
MICRF001
SEL0
0
1
0
1
SEL1
0
0
1
1
QwikRadio
tm
PROGRAMMABLE LPF BANDWIDTH (Hz)
600
1200
2400
4800
Micrel
CTH SOURCE IMPEDANCE (OHMS)
1600k
800k
400k
200k
Table 1.
Nominal Characteristics
Programmable LPF Bandwidth and CTH Source Impedance
CTH Source Impedance in Table 1 is represented by (symbolic) resistor RSC in the MICRF001 Simplified Block Diagram. The
Programmable LPF (Low Pass Filter) is also illustrated in the MICRF001 Simplified Block Diagram.
MICRF001 I
DD
vs Frequency
(Temperature=25°C, V
DD
=5.25V, SWP Mode)
18
16
14
12
10
8
6
4
250
275
300
325
350
375
400
425
450
475
500
I
DD
(mA)
Frequency (MHz)
MICRF001 I
DD
vs Temperature
(Frequency=315MHz, V
DD
=5.25V, SWP Mode)
8.5
8
7.5
7
I
DD
(mA)
6.5
6
5.5
5
-40
-20
0
20
40
60
85
Temperature (C)
June 1998
4
MICRF001
MICRF001
QwikRadio
tm
Micrel
Block Diagram
Functional Description
The block diagram illustrates the basic structure of the
MICRF001. Identified in the figure are the three principal
functional blocks of the IC, namely (1) UHF Downconverter,
(2) OOK Demodulator, and (3) Reference and Control. Also
shown in the figure are two capacitors (CTH, CAGC) and
one timing component (CR), usually a ceramic resonator.
With the exception of a supply decoupling capacitor, these
are all the external components needed with the MICRF001
to construct a complete UHF receiver. Three control inputs
are shown in the block diagram, SEL0, SEL1 and SWEN.
Through these logic inputs the user can control the operating
mode and programmable functions of the IC. These inputs
are CMOS compatible, and are pulled-up on the IC. The
inputs SEL0, SEL1 control the Demodulator filter bandwidth
in four binary steps from approximately 0.6kHz to 4.8kHz,
and the user must select the bandwidth appropriate to his
needs.
The SWEN pin allows the device to be configured in either its
normal (SWP) operating mode, or in standard (FIXED)
superheterodyne receiver mode. SWP operation is selected
when SWEN is HIGH, and is the default mode for the IC. An
example of SWP operation would be where the MICRF001
must operate with LC-based transmitters, whose transmit
frequency may vary up to
±
0.5% over initial tolerance, aging,
and temperature. In this (patent-pending) mode, the LO
frequency is varied in a prescribed fashion which results in
downconversion of all signals in a band 2-3% around the
transmit frequency. So the Transmitter may drift up to
±
0.5% without the need to retune the Receiver, and without
impacting system performance. Such performance is not
achieved
with
currently
available
crystal-based
superheterodyne receivers, which can operate only with
SAW or crystal based transmitters.
[Note: A range penalty will occur in installations where there
exists a competing signal of sufficient strength in this small
frequency band of 2-3%. This penalty also exists with super-
regenerative type receivers, as their RF bandwidth is also
generally 2-3%. So any application for a super-regenerative
receiver is also an application for the MICRF001.]
June 1998
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MICRF001
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