OneNAND256
FLASH MEMORY
OneNAND SPECIFICATION
Product
Part No.
KFG5616Q1M-DEB
OneNAND256
KFG5616D1M-DEB
KFG5616U1M-DIB
V
CC
(core & IO)
1.8V(1.7V~1.95V)
2.65V(2.4V~2.9V)
3.3V(2.7V~3.6V)
Temperature
Extended
Extended
Industrial
PKG
63FBGA(LF)/48TSOP1
63FBGA(LF)/48TSOP1
63FBGA(LF)/48TSOP1
Version: Ver. 1.1
1
OneNAND256
Document Title
OneNAND
FLASH MEMORY
Revision History
Revision No. History
0.0
0.5
Initial issue.
1. Modified to preliminary specification.
2. Add the cache read operation and DQ toggling scheme.
1. Corrected the errata
2. ECC description is revised.
3. Changed Read while Load and Write While Program diagram.
4. Revised OTP Flow Chart
5. Added Multi Block Erase operation cases
6. Added Spare Assignment information
7. Added NAND Array Memory Map
8. Added OTP load/program/lock operation description
9. Revised OTP load/program/lock flow chart ; Excluded the fail case
10. Added Spare Assignment information
11. Added OTP Erase Fail case in Controller Status register output table
12. Added DC/AC parameters
13. Revised OTP area assignment
14. Added INT guidance
15. 2.65V device is added.
1. Corrected the errata
2. Changed Manufacturer ID from 0001h to 00ECh
3. Deleted BootRAM unlock/lock command
4. Revised 1.8V/2.65V/3.3V DC parameters
5. Revised tCES from 9ns to 7ns
6. Write Protection status register description is revised
1. Corrected the errata
2. Moved Interrupt register setting before inputting command in all flow
charts
3. Revised Dual operation diagrams
4. Added and revised the asynchronous read operation timing diagram
5. Revised the asynchronous write operation timing diagram
6. Added the tREADY parameter in Hot Reset operation
7. Revised typical tRD2 from 75us to 50us
8. Revised max tRD2 from 100us to 75us
9. Revised Write Protection status description
1. Revised Cold Reset and Warm Reset diagram
2. Added TSOP1 Package Information
3. Revised typical tOTP, tLOCK from 300us to 600us
4. Revised max tOTP, tLOCK from 600us to 1000us
5. Deleted Lock/Lock-tight All Block Operation
6. Added Endurance and Data Retention
Deleted Confidential Mark
Draft Date
Jan. 6, 2004
Mar. 24, 2004
Remark
Advance
Preliminary
0.6
May. 7, 2004
Preliminary
0.7
July. 6, 2004
Preliminary
0.8
August. 6, 2004
Preliminary
1.0
October. 21, 2004
Final
1.1
December. 17, 2004 Final
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
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OneNAND256
1. FEATURES
•
Design Technology: 0.12µm
•
Voltage Supply
- 1.8V device(KFG5616Q1M) : 1.7V~1.95V
- 2.65V device(KFG5616D1M) : 2.4V~2.9V
- 3.3V device(KFG5616U1M) : 2.7V~3.6V
•
Organization
- Host Interface:16bit
•
Internal BufferRAM(3K Bytes)
- 1KB for BootRAM, 2KB for DataRAM
•
NAND Array
- Page Size : (1K+32)bytes
- Block Size : (64K+2K)bytes
FLASH MEMORY
♦
Architecture
♦
Performance
•
Host Interface type
- Synchronous Burst Read
: Clock Frequency: up to 54MHz
: Linear Burst - 4 , 8 , 16 , 32 words with wrap-around
: Continuous Sequential Burst(512 words)
- Asynchronous Random Read
: Access time of 76ns
- Asynchronous Random Write
•
Programmable Read latency
•
Multiple Sector Read
- Read multiple sectors by Sector Count Register(up to 2 sectors)
•
Multiple Reset
- Cold Reset / Warm Reset / Hot Reset / NAND Flash Reset
•
Power dissipation (typical values, C
L
=30pF)
- Standby current : 10uA@1.8V device, 20uA@2.65V/3.3V device
- Synchronous Burst Read current(54MHz) : 12mA@1.8V device, 25mA@2.65V/3.3V device
- Load current : 10mA@1.8V device, 15mA@2.65V/3.3V device
- Program current: 10mA@1.8V device, 15mA@2.65V/3.3V device
- Erase current: 10mA@1.8V device, 15mA@2.65V/3.3V device
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
♦
Hardware Features
•
Voltage detector generating internal reset signal from Vcc
•
Hardware reset input (RP)
•
Data Protection
- Write Protection mode for BootRAM
- Write Protection mode for NAND Flash Array
- Write protection during power-up
- Write protection during power-down
•
User-controlled One Time Programmable(OTP) area
•
Internal 2bit EDC / 1bit ECC
•
Internal Bootloader supports Booting Solution in system
♦
Software Features
•
Handshaking Feature
- INT pin: Indicates Ready / Busy of OneNAND
- Polling method: Provides a software method of detecting the Ready / Busy status of OneNAND
•
Detailed chip information by ID register
♦
Packaging
•
Package
- 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA
- 48 TSOP 1, 12mm x 20mm, 0.5mm pitch
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OneNAND256
2. GENERAL DESCRIPTION
FLASH MEMORY
OneNAND is a single-die chip with standard NOR Flash interface using NAND Flash Array. This device is comprised of logic and
NAND Flash Array and 3KB internal BufferRAM. 1KB BootRAM is used for reserving bootcode, and 2KB DataRAM is used for buff-
ering data. The operating clock frequency is up to 54MHz. This device is X16 interface with Host, and has the speed of ~76ns random
access time. Actually, it is accessible with minimum 4clock latency(host-driven clock for synchronous read), but this device adopts the
appropriate wait cycles by programmable read latency. OneNAND provides the multiple sector read operation by assigning the num-
ber of sectors to be read in the sector counter register. The device includes one block sized OTP(One Time Programmable), which
can be used to increase system security or to provide identification capabilities.
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OneNAND256
3. PIN DESCRIPTION
Pin Name
Host Interface
A15~A0
I
Address Inputs
- Inputs for addresses during operation, which are for addressing
BufferRAM & Register.
Type
Nameand Description
FLASH MEMORY
DQ15~DQ0
I/O
Data Inputs/Outputs
- Inputs data during program and commands during all operations, outputs data during memory array/
register read cycles.
Data pins float to high-impedance when the chip is deselected or outputs are disabled.
Interrupt
Notifying Host when a command has completed. It is open drain output and does not float to hi-z condi-
tion when the chip is deselected or when outputs are disabled.
Ready
Indicates data valid in synchronous read modes and is activated while CE is low
Clock
CLK synchronizes the device to the system bus frequency in synchronous read mode.
The first rising edge of CLK in conjunction with AVD low latches address input.
Write Enable
WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge
Address Valid Detect
Indicates valid address presence on address inputs. During asynchronous read operation, all addresses
are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on
CLK’s rising edge while AVD is held low for one clock cycle.
> Low : for asynchronous mode, indicates valid address ;for burst mode,
causes starting address to be latched on rising edge on CLK
> High : device ignores address inputs
Reset Pin
When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up
and bootloading.
Chip Enable
CE-low activates internal control logic, and CE-high deselects the device, places it in standby state,
and places ADD and DQ in Hi-Z
Output Enable
OE-low enables the device’s output data buffers during a read cycle.
INT
O
RDY
O
CLK
I
WE
I
AVD
I
RP
I
CE
I
OE
Power Supply
V
CC
-Core
I
Power for OneNAND Core
This is the power supply for OneNAND Core.
Power for OneNAND I/O
This is the power supply for OneNAND I/O
Vcc-IO is internally connected to Vcc-Core, thus should be connected to the same power supply.
Ground for OneNAND
V
CC
-IO
V
SS
etc.
DNU
NC
Do Not Use
Leave it disconnected. These pins are used for testing.
No Connection
Lead is not internally connected.
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