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K7B403225M-TC80

Description
Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100
Categorystorage    storage   
File Size438KB，16 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
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K7B403225M-TC80 Overview

Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100

K7B403225M-TC80 Parametric

Parameter NameAttribute value
MakerSAMSUNG
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time8 ns
Other featuresSELF-TIMED WRITE CYCLE
JESD-30 codeR-PQFP-G100
length20 mm
memory density4194304 bit
Memory IC TypeCACHE SRAM
memory width32
Number of functions1
Number of terminals100
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX32
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
width14 mm

K7B403225M-TC80 Preview

K7B403225M
Document Title
128Kx32-Bit Synchronous Burst SRAM
128Kx32 Synchronous SRAM
Revision History
Rev. No.
1.0
2.0
3.0
History
Initial draft
Modify Rev. No. from 0.0 to 1.0.
Add V
DDQ
Supply voltage( 2.5V )
Draft Date
May. 19. 1998
Jun. 02. 1998
Dec. 02. 1998
Remark
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
December 1998
Rev 3.0
K7B403225M
128Kx32-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
128Kx32 Synchronous SRAM
GENERAL DESCRIPTION
The K7B403225M is 4,194,304 bits Synchronous Static Ran-
dom Access Memory designed to support zero wait state per-
formance for advanced Pentium/Power PC based system. And
with CS
1
high, ADSP is blocked to control signals.
It can be organized as 128K words of 32 bits. And it integrates
address and control registers, a 2-bit burst address counter and
high output drive circuitry onto a single integrated circuit for
reduced components counts implementation of high perfor-
mance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B403225M is implemented with SAMSUNG′s high per-
formance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -75
t
CYC
t
CD
t
OE
8.5
7.5
3.5
-80
10
8
3.5
-90
12
9
3.5
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A
0
~A
1
A
0
~A
16
ADDRESS
REGISTER
A
2
~A
16
A′
0
~A′
1
128Kx32
MEMORY
ARRAY
ADSP
CS
1
CS
2
CS
2
GW
DATA-IN
REGISTER
CONTROL
REGISTER
BW
WEa
WEb
WEc
WEd
OE
ZZ
DQa
0
~ DQd
7
CONTROL
LOGIC
OUTPUT
BUFFER
-2-
December 1998
Rev 3.0
K7B403225M
PIN CONFIGURATION
(TOP VIEW)
128Kx32 Synchronous SRAM
ADSC
ADSP
WEd
WEb
WEa
WEc
ADV
83
CLK
CS
1
CS
2
CS
2
V
DD
GW
V
SS
BW
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A
9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
11
A
12
A
13
A
14
A
15
LBO
N.C.
N.C.
V
SS
N.C.
PIN NAME
SYMBOL
A
0
- A
16
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,
44,45,46,47,48,49,
50,81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
V
DDQ
V
SSQ
PIN NAME
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
TQFP PIN NO.
15,41,65,91
17,40,67,90
1,14,16,30,38,39,42,43,
51,66,80
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
ADV
ADSP
ADSC
CLK
CS
1
CS
2
CS
2
WEx
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
N.C.
V
DD
Output Power Supply
(2.5V or 3.3V)
Output Ground
-3-
A
16
50
N.C.
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
N.C.
V
DD
N.C.
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
N.C.
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
N.C.
December 1998
Rev 3.0
K7B403225M
FUNCTION DESCRIPTION
128Kx32 Synchronous SRAM
The K7B403225M is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power
PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and dura-
tion of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and WEa, WEb, WEc, and WEd are high. When ADSP is sampled low, the chip selects are
sampled active, and the output buffer is enabled with OE. the data of cell array accessed by the current address are projected to the
output pins.
Write cycles are also initiated with ADSP(or ADSC) and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation.
All byte write occurs by enabling GW(independent of BW and WEx.), and individual byte write is performed only when GW is high
and BW is low. In K7B403225M, a 128Kx32 organization, WEa controls DQa0 ~ DQa7 , WEb controls DQb0 ~ DQb7 , WEc controls
DQc0 ~ DQc7 and WEd controls DQd0 ~ DQd7 .
CS
1
is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. And this pin is High, Interleaved burst sequence is selected.
BURST SEQUENCE TABLE
LBO PIN
HIGH
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
0
1
1
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
A
0
0
1
0
1
(Interleaved Burst)
Case 4
A
1
1
1
0
0
A
0
1
0
1
0
Fourth Address
BURST SEQUENCE TABLE
LBO PIN
LOW
First Address
Case 1
A
1
0
0
1
1
A
0
0
1
0
1
A
1
0
1
1
0
Case 2
A
0
1
0
1
0
A
1
1
1
0
0
Case 3
A
0
0
1
0
1
A
1
1
0
0
1
(Linear Burst)
Case 4
A
0
1
0
1
0
Fourth Address
Note :
1. LBO pin must be tied to high or low, and floating state must not be allowed.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2)
:
OPERATION
Sleep Mode
Read
Write
Deselected
ZZ
H
L
L
L
L
OE
X
L
H
X
X
I/O STATUS
High-Z
DQ
High-Z
Din, High-Z
High-Z
Notes
1. X means "Don't Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffersmust
be disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current
does not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
-4-
December 1998
Rev 3.0
K7B403225M
SYNCHRONOUS TRUTH TABLE
CS
1
H
L
L
L
L
L
L
L
X
H
X
H
X
H
X
H
CS
2
X
L
X
L
X
H
H
H
X
X
X
X
X
X
X
X
CS
2
X
X
H
X
H
L
L
L
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
X
X
L
H
H
H
X
H
X
H
X
H
X
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
L
L
L
L
H
H
H
H
WRITE
X
X
X
X
X
X
L
H
H
H
L
L
H
H
L
L
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
128Kx32 Synchronous SRAM
ADDRESS ACCESSED
N/A
N/A
N/A
N/A
N/A
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
OPERATION
Not Selected
Not Selected
Not Selected
Not Selected
Not Selected
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
Notes :
1. X means "Don
′
t Care".
2. The rising edge of clock is symbolized by
↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
H
H
H
H
H
H
L
BW
H
L
L
L
L
L
X
WEa
X
H
L
H
H
L
X
WEb
X
H
H
L
H
L
X
WEc
X
H
H
H
L
L
X
WEd
X
H
H
H
L
L
X
OPERATION
READ
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c and d
WRITE ALL BYTEs
WRITE ALL BYTEs
Notes :
1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
-5-
December 1998
Rev 3.0
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

K7B403225M-TC80 Related Products

K7B403225M-TC80 K7B403225M-QC900 K7B403225M-QC750 K7B403225M-TC90 K7B403225M-TC75 K7B403225M-QC800
Description Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 Cache SRAM, 128KX32, 9ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 Cache SRAM, 128KX32, 9ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 Cache SRAM, 128KX32, 8ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100
Maker SAMSUNG SAMSUNG SAMSUNG SAMSUNG SAMSUNG SAMSUNG
Parts packaging code QFP QFP QFP QFP QFP QFP
package instruction LQFP, LQFP, LQFP, LQFP, LQFP, LQFP,
Contacts 100 100 100 100 100 100
Reach Compliance Code unknown unknown unknown unknown unknow unknow
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Maximum access time 8 ns 9 ns 7.5 ns 9 ns 7.5 ns 8 ns
JESD-30 code R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100 R-PQFP-G100
length 20 mm 20 mm 20 mm 20 mm 20 mm 20 mm
memory density 4194304 bit 4194304 bit 4194304 bit 4194304 bit 4194304 bi 4194304 bi
Memory IC Type CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM
memory width 32 32 32 32 32 32
Number of functions 1 1 1 1 1 1
Number of terminals 100 100 100 100 100 100
word count 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words
character code 128000 128000 128000 128000 128000 128000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
organize 128KX32 128KX32 128KX32 128KX32 128KX32 128KX32
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP LQFP LQFP LQFP LQFP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD
width 14 mm 14 mm 14 mm 14 mm 14 mm 14 mm

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Shortcut:   00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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