EEWORLDEEWORLDEEWORLD

Part Number

Search

868602

Description
Board Connector, 2 Contact(s), 1 Row(s), Male, Straight, Solder Terminal,
CategoryThe connector    The connector   
File Size61KB,1 Pages
ManufacturerMolex
Websitehttps://www.molex.com/molex/home
Download Datasheet Parametric View All

868602 Overview

Board Connector, 2 Contact(s), 1 Row(s), Male, Straight, Solder Terminal,

868602 Parametric

Parameter NameAttribute value
MakerMolex
Reach Compliance Codeunknown
ECCN codeEAR99
Connector typeBOARD CONNECTOR
Contact point genderMALE
DIN complianceNO
Filter functionNO
IEC complianceNO
MIL complianceNO
Manufacturer's serial number39860
Mixed contactsNO
Installation methodSTRAIGHT
Installation typeBOARD
Number of rows loaded1
OptionsGENERAL PURPOSE
Terminal pitch5.08 mm
Termination typeSOLDER
Total number of contacts2
UL Flammability Code94V-0
FPGA process block trigger
I recently read an article that said that in FPGA, it is best to trigger all process blocks with the system clock. For example, when the digital tube is dynamically displayed, the frequency of the sel...
lupengpeng FPGA/CPLD
[STM32F7 League of Legends Competition] Reflective blood oxygen heart rate signal acquisition and monitoring recording system-design summary
[i=s]This post was last edited by nemo1991 on 2016-3-5 20:39[/i] [align=left][align=left]Time flies. I saw the event on forum F7 at the beginning of the semester and decided to participate. It took me...
nemo1991 stm32/stm8
Wuhan Yitiannuo is recruiting sales engineers
[align=center][font=微软雅黑][size=6]Wuhan Yitiannuo sincerely recruits sales engineers[/size][/font][/align] [b]Job responsibilities:[/b][p=25, 2, left]1. Regularly complete the sales tasks assigned by t...
LunaEternal Talking about work
Schedule of the 2015 National Undergraduate Electronic Design Competition
[align=left][size=5][color=#0000ff]The national competition is about to begin! If you are still unclear about the specific arrangements for the national competition, please check it out [/color][/size...
wsxzaq Electronics Design Contest
LVDS Receive
I am using Cyclone V FPGA to receive 8-channel differential data, 12bit, 600M data rate. The data received by LVDS_RX core is incorrect. The 8-channel data is not synchronized. Can anyone tell me how ...
BIT_Wang FPGA/CPLD
sqlce connection failed
代码:string strConn = "Data Source=" + sDbpath + ";Password=SZTL";m_Conn = new SqlCeConnection(strConn);m_Conn.Open(); 异常: 未处理 System.Data.SqlServerCe.SqlCeExceptionMessage="Unspecified error"HResult=-2...
jingon Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2150  46  1990  2387  384  44  1  41  49  8 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号