a
FEATURES
14-Bit 30 MSPS A/D Converter
30 MSPS Correlated Double Sampler (CDS)
4 dB 6 dB 6-Bit Pixel Gain Amplifier (PxGA
®
)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 153 mW @ 3 V Supply
Space-Saving 48-Lead LFCSP Package
APPLICATIONS
High Performance Digital Still Cameras
Industrial/Scientific Imaging
Complete 14-Bit 30 MSPS
CCD Signal Processor
AD9824
PRODUCT DESCRIPTION
The AD9824 is a complete analog signal processor for CCD
applications. It features a 30 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9824’s signal chain
consists of an input clamp, a correlated double sampler (CDS),
PxGA,
a digitally controlled VGA, a black level clamp, and a
14-bit A/D converter. Additional input modes are also pro-
vided for processing analog video signals.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input configuration, and
power-down modes.
The AD9824 operates from a single 3 V power supply, typically
dissipates 153 mW, and is packaged in a 48-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
HD
VD
VRT
VRB
PBLK
4dB
CCDIN
CDS
6dB
COLOR
STEERING
2dB~36dB
2:1
MUX
VGA
BAND GAP
REFERENCE
DRVDD
DRVSS
PxGA
ADC
14
DOUT
CLP
6
CLPDM
10
AUX1IN
2:1
MUX
AUX2IN
CLP
CONTROL
REGISTERS
BUF
8
BLK CLAMP
LEVEL
CLPOB
CLP
DVDD
AD9824
DIGITAL
INTERFACE
INTERNAL
TIMING
DVSS
SL
SCK
SDATA
SHP
SHD
DATACLK
PxGA
is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9824–SPECIFICATIONS
GENERAL SPECIFICATIONS
(T
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
POWER CONSUMPTION
Normal Operation
Power-Down Modes
Standby
Total Power-Down
MAXIMUM CLOCK RATE
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Data Output Coding
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
Specifications subject to change without notice.
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
Min
–20
–65
2.7
Typ
Max
+85
+150
3.6
Unit
°C
°C
V
(Specified Under Each Mode of Operation)
5
0.5
30
14
±
0.5
14
2.0
Straight Binary
2.0
1.0
±
1.0
mW
mW
MHz
Bits
LSB
Bits Guaranteed
V
V
V
DIGITAL SPECIFICATIONS
(DRVDD = 2.7 V, C = 20 pF, unless otherwise noted.)
L
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA
Low Level Output Voltage, I
OL
= 2 mA
Specifications subject to change without notice.
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
Min
2.1
Typ
Max
Unit
V
V
µA
µA
pF
V
V
0.6
10
10
10
2.2
0.5
–2–
REV. 0
AD9824
CCD-MODE SPECIFICATIONS
(T
Parameter
P
OWER CONSUMPTION
MAXIMUM CLOCK RATE
CDS
Gain
Allowable CCD Reset Transient
1
Max Input Range Before Saturation
1
Max CCD Black Pixel Amplitude
1
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range (Two’s Complement Coding)
Min Gain (PxGA Gain Code 32)
Max Gain (PxGA Gain Code 31)
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (VGA Gain Code 77)
Max Gain (VGA Gain Code 1023)
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
SYSTEM PERFORMANCE
Gain Accuracy
2
Low Gain (VGA Code 77)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
POWER-UP RECOVERY TIME
Reference Standby Mode
Total Shutdown Mode
Power-Off Condition
NOTES
1
Input signal characteristics defined as follows:
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= f
SHP
= f
SHD
= 30 MHz, unless otherwise noted.)
Typ
153
Min
Max
Unit
mW
MHz
Notes
See TPC 1 for Power Curves
30
0
500
1.0
200
1.0
1.6
64
Guaranteed
–2.5
9.5
1.6
2.0
1024
Guaranteed
2
36
256
0
1020
dB
mV
V p-p
mV
V p-p
V p-p
Steps
See Input Waveform in Footnote 1
PxGA
Gain at 4 dB
See Figure 28 for
PxGA
Gain Curve
dB
dB
V p-p
V p-p
Steps
See Figure 29 for VGA Gain Curve
dB
dB
Steps
Measured at ADC Output
LSB
LSB
Specifications Include Entire Signal Chain
Gain = (0.0353
×
Code) +3.3
5.5
38.2
6
39.4
0.1
2.0
40
1
3
15
6.5
40.2
dB
dB
%
LSB rms
dB
ms
ms
ms
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
Normal Clock Signals Applied
500mV TYP
RESET TRANSIENT
200mV MAX
OPTICAL BLACK PIXEL
2
1V MAX
INPUT SIGNAL RANGE
PxGA
gain fixed at Code 63 (3.3 dB).
Specifications subject to change without notice.
REV. 0
–3–
AD9824–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS
(T
Parameter
POWER CONSUMPTION
MAXIMUM CLOCK RATE
INPUT BUFFER
Gain
Max Input Range
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
Max Gain
Specifications subject to change without notice.
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
Min
Typ
120
30
0
1.0
2.0
1023
0
36
Max
Unit
mW
MHz
dB
V p-p
V p-p
Steps
dB
dB
AUX2-MODE SPECIFICATIONS
Parameter
POWER CONSUMPTION
MAXIMUM CLOCK RATE
INPUT BUFFER
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
Max Gain
ACTIVE CLAMP
Clamp Level Resolution
Clamp Level (Measured at ADC Output)
Min Clamp Level
Max Clamp Level
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
Min
Typ
120
30
(Same as AUX1-MODE)
2.0
512
0
18
256
0
1020
V p-p
Steps
dB
dB
Steps
LSB
LSB
Max
Unit
mW
MHz
–4–
REV. 0
AD9824
TIMING SPECIFICATIONS
Parameter
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth
*
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
Specifications subject to change without notice.
(C
L
= 20 pF, f
SAMP
= 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7,
Serial Timing in Figures 21–24.)
Symbol
t
CP
t
ADC
t
SHP
t
SHD
t
CDM
t
COB
t
S1
t
S2
t
ID
t
INH
t
OD
t
H
Min
33
13
5
5
4
2
0
15
10
13
7.6
9
16
Typ
33
16.7
8.3
8.3
10
20
8.3
16.7
3.0
Max
Unit
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns
7.0
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
10
10
10
10
10
10
*
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
ABSOLUTE MAXIMUM RATINGS
With
Respect
To
Min Max
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+3.9
+3.9
+3.9
DRVDD + 0.3
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
300
ORDERING GUIDE
Model
Unit
V
V
V
V
V
V
V
V
V
°C
°C
Temperature
Range
–20°C to +85°C
Package
Description
LFCSP
Package
Option
CP-48
Parameter
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-3, CCDIN
Junction Temperature
Lead Temperature (10 sec)
AD9824KCP
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LFCSP Package
θ
JA
= 26°C/W*
*
θ
JA
is measured using a 4-layer PCB with the exposed paddle
soldered to the board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9824 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
京公网安备 11010802033920号
EEWORLD
