WM8170
3.3V Integrated Signal Processor for Area Array CCDs
Product Preview Rev 1.0 March 2000
DESCRIPTION
The WM8170 is a 10-bit analogue front end/digitiser IC,
which processes and digitises the analogue output signals
from area array CCD sensors at pixel sample rates of up to
21MSPS.
The device contains input blanking, correlated double
sampling (CDS), programmable gain amplifier, black level
clamp, on-board voltage reference and a 10-bit, 21MSPS
ADC. Two auxiliary 8 bit DACs are provided which may be
used for bias voltage control or camera functions such as
auto-focus.
Fine black level adjustment is performed digitally after the
ADC. This digital adjustment will follow DC shifts in the video
input without introducing digital correction noise into the
image.
The WM8170 is designed to interface to a wide range of area
array CCDs and can operate at lower power for slower
sample rates by setting the reference bias current via an
external resistor connected to the ISET pin.
All signal timing within the device is derived from the CCD
clock signals. The WM8170 is controlled via a configurable
serial interface, which is compatible with all of Wolfson’
s
imaging devices.
The user is able to control the device functions and monitor
on-chip register settings via the easy-to-use digital
management interface.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
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10-bit, 21MSPS ADC
No missing codes guaranteed
Correlated double sampling
Programmable gain amplifier
Black level clamp
Input blanking
Two auxiliary 8-bit DACs
Power save mode
Serial or parallel control bus
Adjustable sample rate
User selectable sampling on rising or falling edge
of clocks
Single 3.3V power supply (3V minimum)
48-pin TQFP package
Standby mode I
CC
<10µA
Power consumption typically 190mW at 12MHz,
270mW at 21MHz
APPLICATIONS
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Digital still cameras
Digital camcorders
PC cameras
Progressive scan CCDs
NTSC, PAL interline CCDs
BLOCK DIAGRAM
VRB VMID VRT
(15) (16) (14)
BLCENB
(27)
SHP SHD
(22) (21)
CVDD
(42)
AVDD[1-3] DVDD[1-4] DCLK
(10,11,20) (3,23,33,39) (38)
VCLP (12)
REFERENCE
CLPENB (24)
CLPSWB (25)
PIN (19)
DIN (18)
PBLK/HD (26)
Dual Mode Pin
ANALOGUE
BLACK
LEVEL
CLAMP
TIMING GENERATOR
DIGITAL
COMPARATOR
DIGITAL
BLACK
LEVEL
CLAMP
AND
FILTER
(8) PTDO
(31) OEB
CLAMP
CDS
S/H
PGA
10-BIT
ADC
HI-Z
DATA I/O
(1,4-7,44-48)
VOUT1 (40)
8-BIT
ADC
8-BIT
ADC
WM8170
CONFIGURABLE
SERIAL/PARALLEL
INTERFACE
(29) PNS
(36) SEN/STB
(37) SCK/RNW
(35) SDI/DNA
(32) NRESET
(34) SDO
(30) PDB/VD
Dual Mode Pin
VOUT2 (41)
BIAS
CIRCUIT
(43)
CGND
(9,17)
AGND[1-2]
(13)
ISET
(2,28)
DGND[1-2]
WOLFSON MICROELECTRONICS LTD.
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Product Preview
data sheets contain
specifications for products in the formative
phase of development. These products may
be changed or discontinued without notice.
©
2000 Wolfson Microelectronics Ltd
.
WM8170
PIN CONFIGURATION
SCL/RNW
DVDD1
DCLK
VOUT2
VOUT1
Product Preview Rev 1.0
ORDERING INFORMATION
DEVICE
TEMP. RANGE
0 to 70
o
C
PACKAGE
48-pin TQFP
XWM8170CFT/V
CGND
D5
DGND2
DVDD4
D6
D7
D8
D9
PTDO
AGND1
AVDD1
AVDD3
VCLP
1
2
3
4
5
6
7
8
9
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
CVDD
D4
D3
D2
D1
D0
SEN/STB
SDI/DNA
SDO
DVDD3
NRESET
OEB
PDB/HD
PNS
DGND1
BLCENB
PBLK/HD
CLPSWB
WM8170
10
11
12
25
13 14 15 16 17 18 19 20 21 22 23 24
VRB
VMID
PIN
AVDD2
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating
at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under
Electrical Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during
handling and storage of this device.
As per JEDEC specifications A112-A and A113-A this product requires specific storage conditions prior to surface mount
assembly and as such will be supplied in vacuum sealed moisture barrier bags.
CONDITION
Analogue supply voltages (AVDD1 to AVDD3)
Digital supply voltages (DVDD1 to DVDD4)
Clock supply voltage, CVDD
Digital inputs BLCENB, CLPENB, CLPSWB, PBLK, SHD, SHP pins
Digital inputs PDB, NRESET, SCK/RNW, SEN/STB, PNS, SDI/DNA,
OEB, DCLK, SDO pins
Digital outputs, D0 to D9, PTDO
Analogue inputs and analogue outputs
Maximum difference between AGND, DGND and CGND
Maximum difference between DVDD1, AVDD and CVDD
Operating temperature range, T
A
Storage temperature
Lead temperature (soldering, 10 seconds)
Note 1:
CLPENB
AGND2
DIN
SHP
DVDD2
ISET
VRT
SHD
MIN
AGND -0.3V
DGND -0.3V
CGND -0.3V
DGND -0.3V
DGND -0.3V
DGND -0.3V
AGND -0.3V
- 0.1V
- 0.1V
0C
-65 C
o
o
MAX
AGND +7V
DGND +7V
CGND +7V
DVDD2 +0.3V
DVDD3 +0.3V
DVDD4 +0.3V
AVDD +0.3V
+0.1V
+0.1V
+70 C
+150 C
+260 C
o
o
o
Note 2:
AGND denotes the voltage on any analogue ground pin.
DGND denotes the voltage on any digital ground pin.
CGND denotes the voltage on the clock ground pin.
For this device all GND pins should be star connected as close as possible to the device.
AVDD denotes the voltage on any AVDD pin.
For this device all AVDD supplies should be connected together.
PP Rev 1.0 March 2000
WOLFSON MICROELECTRONICS LTD
2
WM8170
Product Preview Rev 1.0
RECOMMENDED OPERATING CONDITIONS
SHD/SHP = 21MHz RISET=15kΩ
PARAMETER
Supply voltage
Analogue supply current - active
Digital supply current - active
(Note 1)
Clock supply current - active
Supply current - standby (Total)
I
AACT
I
DACT
I
CACT
I
SDBY
SHD/SHP = 0MHz
SYMBOL
TEST CONDITIONS
MIN
2.97
68
8
6
10
10
TYP
MAX
3.63
80
UNIT
V
mA
mA
mA
µA
SHD/SHP = 12MHz RISET=22kΩ
PARAMETER
Supply voltage
Analogue supply current - active
Digital supply current - active
(Note 1)
Clock supply current - active
Supply current – standby (Total)
Note 1:
I
AACT
I
DACT
I
CACT
I
SDBY
SHD/SHP = 0MHz
SYMBOL
TEST CONDITIONS
MIN
2.97
50
4
4
10
TYP
MAX
3.63
UNIT
V
mA
mA
mA
µA
Digital supply current - active includes DVDD4 current, which is dependent on the D[9:0] capacitive load.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
3
WM8170
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
D5
DGND2
DVDD4
D6
D7
D8
D9
PTDO
AGND1
AVDD1
AVDD3
VCLP
ISET
VRT
VRB
VMID
AGND2
DIN
PIN
AVDD2
SHD
SHP
DVDD2
CLPENB
CLPSWB
PBLK/HD
BLCENB
DGND1
PNS
PDB/VD
OEB
NRESET
DVDD3
SDO
SDI/DNA
SEN/STB
SCK/RNW
DCLK
DVDD1
VOUT1
VOUT2
CVDD
CGND
D0
D1
D2
D3
D4
NAME
Digital IO
Supply
Supply
Digital IO
Digital IO
Digital IO
Digital IO
Digital output
Supply
Supply
Supply
Analogue output
Analogue output
Analogue output
Analogue output
Analogue output
Supply
Analogue input
Analogue input
Supply
Digital input
Digital input
Supply
Digital input
Digital input
Digital input
Digital input
Supply
Digital input
Digital input
Digital input
Digital input
Supply
Digital tri-stateable output
Digital input
Digital input
Digital input
Digital input
Supply
Analogue output
Analogue output
Supply
Supply
Digital output
Digital output
Digital IO
Digital IO
Digital IO
TYPE
DESCRIPTION
Data output 5/parallel data IO3
Digital ground for D0 to D9, PTDO pins
Digital supply for D0 to D9, PTDO pins
Data output 6/parallel data IO4
Data output 7/parallel data IO5
Data output 8/parallel data IO6
Data output 9 (MSB)/parallel data IO7
Programmable threshold detect output
Analogue ground and device substrate
Analogue supply for ADC
Analogue supply for references, bias voltage
Reset level clamping voltage output
External resistor for bias current control
Upper ADC reference voltage output
Lower ADC reference voltage output
Midrail reference voltage output
Analogue ground and device substrate
Video data input
Video preset input
Product Preview Rev 1.0
Analogue supply for S/H, PGA, analogue DC correction loop and
auxiliary DACs
Sample and Hold data control
Sample and Hold preset control
Digital supply BLCENB, CLPENB, CLPSWB, PBLK, SHD, SHP pins
Reset level clamp enable input, active low
Reset level clamp enable switch, active low
Input blocking control, active low/Horizontal drive timing signal input
Black level clamp control, active low
Digital ground for DVDD1, DVDD2, DVDD3 supplies
Parallel not serial control
External power down, active low/Vertical drive timing signal input
Output enable bar, active low
Master chip reset, active low
Digital supply for PDB, NRESET, SCK/RNW, SEN/STB, PNS,
SDI/DNA, OEB, DCLK, SDO pins
Serial data output, tri-stateable
Serial data in/parallel data not address (management interface)
Serial enable/parallel strobe (management interface)
Serial clock/parallel read not write (management interface)
Output data retiming clock input
Digital supply for internal logic
Auxiliary DAC1 output
Auxiliary DAC2 output
Positive supply for internal clock generation circuitry
Ground for internal clock generation circuitry
Data output 0 (LSB), tri-stateable
Data output 1, tri-stateable
Data output 2/parallel data IO0
Data output 3/parallel data IO1
Data output 4/parallel data IO2
PP Rev 1.0 March 2000
WOLFSON MICROELECTRONICS LTD
4
WM8170
Product Preview Rev 1.0
ELECTRICAL CHARACTERISTICS
Test Characteristics
CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15kΩ , TA = 0
o
C to +70
o
C, unless otherwise stated.
PARAMETER
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital Outputs
High level output voltage
Low level output voltage
High impedance O/P current
Analogue Inputs
Input common mode range
Resolution
Maximum differential non-
linearity
Maximum integral non-
linearity
Maximum sampling rate
CDS S/H
Maximum input voltage for
full scale ADC output
V
INMAX
PGA = 00hex
V375
TIMES2
0
0
0
1
1
0
1
1
PGA = FFhex
V375
TIMES2
0
0
0
1
1
0
1
1
TIMES2=0, V375=1
TIMES2=1, V375=1
TIMES2=0, V375=1
TIMES2=1, V375=1
5
27
33
8
P
DNL
P
INL
DNL
INL
S
MAX
PGA at minimum gain
PGA at minimum gain
21.5
+/-2
V
CMR
0.3
10
+/-1
AVDD-0.3
V
Bits
LSB
LSB
MSPS
10-bit ADC Performance Including CDS and PGA Functions NO MISSING CODES GUARANTEED
V
OH
V
OL
I
OZ
I
OH
= 1mA
I
OL
= 1mA
DVDD-0.6
0.6
1
V
V
µA
V
IH
V
IL
I
IH
I
IL
C
IN
5
0.8*DVDD
0.2*DVDD
1
1
V
V
µA
µA
pF
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
0.5
1.5
0.75
V
V
V
V
Minimum input voltage for full
scale ADC output
V
INMIN
40
20
60
30
0
6
28
34
0.11
7
29
35
mV
mV
mV
mV
dB
dB
dB
dB
dB
Bits
LSB
LSB
PGA
Minimum gain
Minimum gain
Maximum gain
Maximum gain
LSB step size
Resolution
PGA maximum differential
non-linearity
PGA maximum integral
non-linearity
G
NTMIN
G
TMIN
G
NTMAX
G
TMAX
G
LSB
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 March 2000
5
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