WM2617
Dual 10-Bit Serial DAC with Power Down
Production Data, Rev 1.1, October 2000
FEATURES
•
•
•
•
•
•
Two 10-bit DACs
Single supply from 2.7V to 5.5V supply operation
DNL
±0.1
LSB, INL
±0.5
LSB
Low power consumption
•
3mW typical in slow mode
•
8mW typical in fast mode
TMS320, (Q)SPI, and Microwire compatible serial
interface
Programmable settling time 4µs or 12µs typical
DESCRIPTION
The WM2617 is a dual 10-bit voltage output, resistor string,
digital-to-analogue converter. A power-on-reset function
ensures repeatable start-up conditions.
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2617 is programmed with a 16-bit serial word.
The WM2617 has a simple-to-use single 2.7V to 5.5V supply.
The digital inputs feature Schmitt triggers for high noise
immunity.
The number of clocks from the falling edge of NCS are counted
automatically. The device is then updated and disabled from
accepting further data inputs.
Excellent performance is delivered with a typical DNL of ±0.1
LSBs. The settling time of the DAC is programmable to allow
the designer to optimise speed versus power dissipation.
The device is available in an 8-pin SOIC package ideal for
space-critical applications. Commercial temperature (0° to
70°C) and industrial temperature (-40° to 85°C) variants are
supported.
APPLICATIONS
•
•
•
•
•
•
•
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
WM2617CD
WM2617ID
TEMP. RANGE
0° to 70°C
-40° to 85°C
PACKAGE
8-pin SOIC
8-pin SOIC
BLOCK DIAGRAM
VDD
(8)
REFIN(6)
REFERENCE
INPUT BUFFER
X1
DAC
OUTPUT
BUFFER
TYPICAL PERFORMANCE
0.25
VDD = 5V, V
REF
= 2.048V, Speed = Fast mode, Load = 10K/100pF
0.2
0.15
0.1
DNL - LSB
(4) OUTA
DIN (1)
data
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
10-BIT
DAC A
LATCH
REFERENCE
INPUT BUFFER
X1
X2
0.05
0
-0.05
-0.1
SCLK (2)
NCS (3)
DAC
OUTPUT
BUFFER
X2
(7) OUTB
10-BIT
DAC B
HOLDING
LATCH
10-BIT
DAC B
CONTROL
LATCH
-0.15
-0.2
POWER-ON
RESET
2-BIT
CONTROL
LATCH
POWERDOWN/
SPEED
CONTROL
-0.25
0
256
512
DIGITAL CODE
767
1023
WM2617
(5)
AGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: sales@wolfson.co.uk
http://www.wolfson.co.uk
Production Data
datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and Conditions.
2000
Wolfson Microelectronics Ltd
.
WM2617
Production Data
PIN CONFIGURATION
DIN
SCLK
NCS
OUTA
1
2
3
4
8
7
6
5
VDD
OUTB
REFIN
AGND
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
NAME
DIN
SCLK
NCS
OUTB
AGND
REFIN
OUTA
VDD
TYPE
Digital input
Digital input
Digital input
Analogue output
Supply
Analogue input
Analogue output
Supply
Serial data input.
Serial clock input.
Chip select, active low.
DAC B analogue output.
Analogue ground.
Reference voltage input.
DAC A analogue output.
Positive power supply.
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
Supply voltage, VDD to AGND
Digital input voltage
Reference input voltage
Operating temperature range, T
A
Storage temperature
Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds
WM2617CD
WM2617ID
-0.3V
-0.3V
0°C
-40°C
-65°C
MIN
MAX
7V
VDD + 0.3V
VDD + 0.3V
70°C
85°C
150°C
260°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage
High-level digital input voltage
Low-level digital input voltage
Reference voltage to REFIN
Load resistance
Load capacitance
Serial Clock Rate
Operating free-air temperature
SYMBOL
VDD
V
IH
V
IL
V
REF
R
L
C
L
f
SCLK
T
A
WM2637CD
WM2637ID
0
-40
2
100
20
70
85
°C
°C
VDD = 5V
VDD = 5V
TEST CONDITIONS
MIN
2.7
2
0.8
VDD - 1.5
TYP
MAX
5.5
UNIT
V
V
V
V
kΩ
Note:
Reference voltages greater than VDD/2 will cause saturation for large DAC codes.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
2
WM2617
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions:
R
L
= 10kΩ, C
L
= 100pF. VDD = 5V
±
10%, V
REF
= 2.048V and VDD = 3V
±
10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise)
PARAMETER
Static DAC Specifications
Resolution
Integral non-linearity
Differential non-linearity
Zero code error
Gain error
D.c. power supply rejection ratio
Zero code error temperature coefficient
Gain error temperature coefficient
DAC Output Specifications
Output voltage range
Output load regulation
Power Supplies
Active supply current
I
DD
No load, V
IH
= VDD, V
IL
= 0V
VDD = 5.5V, V
REF
= 2.048V Slow
VDD = 5.5V, V
REF
= 2.048V Fast
See Note 8
No load,
all digital inputs 0V or VDD
DAC code 32 to 1023, 10%-90%
Slow
Fast
See Note 9
DAC code 32 to 1023
Slow
Fast
See Note 10
Code 511 to 512
0.6
1.6
0.01
1.0
2.5
mA
mA
µA
2kΩ to 10kΩ load
See Note 7
0
0.1
VDD - 0.1
0.3
V
%
INL
DNL
ZCE
GE
DC PSRR
See Note 1
See Note 2
See Note 3
See Note 4
See Note 5
See Note 6
See Note 6
10
bits
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±
1
±
0.1
3
0.1
0.5
10
10
LSB
LSB
mV
% FSR
mV/V
ppm/°C
ppm/°C
±
0.5
±
12
±
0.6
Power down supply current
Dynamic DAC Specifications
Slew rate
0.3
2.4
0.5
3.0
V/µs
V/µs
Settling time
12
4
10
µs
µs
nV-s
Glitch energy
Reference
Reference input resistance
Reference input capacitance
Reference feedthrough
Reference input bandwidth
R
REFIN
C
REFIN
10
5
V
REF
= 1VPP at 1kHz
+ 1.024V dc, DAC code 0
V
REF
= 0.2VPP + 1.024V dc
DAC code 512
Slow
Fast
-60
MΩ
pF
dB
0.5
1.0
1
-1
8
MHz
MHz
µA
µA
pF
Digital Inputs
High level input current
Low level input current
Input capacitance
I
IH
I
IL
C
I
Input voltage = VDD
Input voltage = 0V
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
3
WM2617
Production Data
Notes:
Integral non-linearity (INL)
is the maximum deviation of the output from the line between zero and full scale (excluding
1.
the effects of zero code and full scale errors).
Differential non-linearity (DNL)
is the difference between the measured and ideal 1LSB amplitude change of any
2.
adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains
constant) as a change in digital input code.
3.
Zero code error
is the voltage output when the DAC input code is zero.
Gain error
is the deviation from the ideal full scale output excluding the effects of zero code error.
4.
5.
Power supply rejection ratio
is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6.
Zero code error
and
Gain error
temperature coefficients are normalised to full scale voltage.
7.
Output load regulation
is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is
expressed as a percentage of the full scale output voltage with a 10kΩ load.
8.
I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7Vsupply current will
increase.
9.
Slew rate
results are for the lower value of the rising and falling edge slew rates.
10.
Settling time
is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
SERIAL INTERFACE
t
SUCSS
NCS
t
WCL
SCLK
t
SUDCLK
DIN
D15
D14
t
HDCLK
D13
D12
D11
D0
t
WCH
t
SUCS1
t
SUCS2
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10kΩ, C
L
= 100pF. VDD = 5V
±
10%, V
REF
= 2.048V and VDD = 3V
±
10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise)
SYMBOL
t
SUCSS
t
SUCS1
t
SUCS2
t
WCH
t
WCL
t
SUDCLK
t
HDCLK
TEST CONDITIONS
Setup time NCS low before SCLK low
Setup time, falling edge of SCLK to rising edge of
NCS, external end of write
Setup time, rising edge of SCLK to falling edge of
NCS, start of next write cycle
Pulse duration, SCLK high
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
MIN
5
10
5
25
25
5
5
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
4
WM2617
Production Data
TYPICAL PERFORMANCE GRAPHS
3
VDD = 5V, V
REF
= 2.048V, Speed = Fast mode, Load = 10K/100pF
2
1
INL - LSB
0
-1
-2
-3
0
256
512
DIGITAL CODE
767
1023
Figure 2 Integral Non-Linearity
0.4
0.4
VDD = 3V, V
REF
= 1V, Input Code = 0
0.35
0.35
VDD = 5V, V
REF
= 2V, Input Code = 0
0.3
0.3
OUTPUT VOLTAGE - V
OUTPUT VOLTAGE - V
0.25
0.25
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
0
0
1
2
3
4
5
ISINK- mA
6
7
8
9
Slow
0
10
Fast
0
1
2
3
4
5
ISINK - mA
6
7
8
9
Slow
10
Fast
Figure 3 Sink Current VDD = 3V
2.06
Figure 4 Sink Current VDD = 5V
4.1
VDD = 3V, V
REF
= 1V, Input Code = 4095
2.055
VDD = 5V, V
REF
= 2V, Input Code = 4095
4.095
2.05
4.09
2.045
OUTPUT VOLTAGE - V
0
1
2
3
4
5
6
7
8
9
10
Slow
OUTPUT VOLTAGE - V
4.085
2.04
4.08
2.035
4.075
2.03
4.07
2.025
4.065
2.02
11
Fast
ISOURCE- mA
4.06
0
1
2
3
4
5
6
7
8
9
10
Slow
11
Fast
ISOURCE - mA
Figure 5 Source Current VDD = 3V
Figure 6 Source Current VDD = 5V
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 October 2000
5
京公网安备 11010802033920号
EEWORLD
