54DX
CY7C954DX
ATM HOTLink® Transceiver
Features
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Second-generation HOTLink® technology
UTOPIA level I and II compatible host bus interface
Three-bit Multi-PHY address capability built-in
Three user-selectable Start Of Cell marker/indicators
Embedded 256-character synchronous FIFOs
Built-in ATM Header Error Control (HEC)
Automatic Transmit-HEC insertion & Receiver-HEC
check
FIFO cell-level flushing of invalid ATM cells
ATM Forum, Fibre Channel, and ESCON® compliant
8B/10B encoder/decoder
50- to 200-MBaud serial signaling rate
Internal PLLs with no external PLL components
Dual differential PECL-compatible serial inputs
Dual differential PECL-compatible serial outputs
Compatible with fiber-optic modules and copper cables
Built-In Self-Test (BIST) for link testing
Link Quality Indicator
Single +5.0V
±10%
supply
100-pin TQFP
0.35µ CMOS technology
technology, functionality, and integration over the field proven
CY7B923/933 HOTLink.
The transmit section of the CY7C954DX HOTLink has been
configured to accept 8-bit data characters on each clock cycle,
and store the parallel data into an internal Transmit FIFO. Data
is read from the Transmit FIFO and is encoded using an em-
bedded 8B/10B encoder to improve its serial transmission
characteristics. These encoded characters are then serialized
and output from two Pseudo ECL (ECL referenced to +5.0V)
compatible differential transmission line drivers at a bit-rate of
10 times the input reference clock.
The receive section of the CY7C954DX HOTLink accepts a
serial bit-stream from one of two PECL-compatible differential
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for
data reconstruction. The recovered bit stream is deserialized
and framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are re-
constructed into 8-bit data characters, written to an internal
Receive FIFO, and presented to the destination host system.
For those systems requiring even greater FIFO storage capa-
bility, external FIFOs may be directly coupled to the
CY7C954DX device through the parallel interface without ad-
ditional glue-logic for single PHY connections.
The TTL parallel I/O interface may be configured as either a
FIFO (configurable for UTOPIA emulation or for depth expan-
sion through external FIFOs) or as a pipeline register extender.
The FIFO configurations are optimized for transport of time-
independent (asynchronous) 8-bit character-oriented data
across a link. A Built-In Self-Test (BIST) pattern generator and
checker allows for at-speed testing of the high-speed serial
data paths in both the transmit and receive sections, and
across the interconnecting links.
HOTLink devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed, point-to-
point serial links. Some applications include interconnecting
workstations, backplanes, servers, mass storage, and video
transmission equipment.
Functional Description
The 200-MBaud CY7C954DX HOTLink Transceiver is a point-
to-point communications building block allowing the transfer of
data over high-speed serial links (optical fiber, balanced, and
unbalanced copper transmission lines) at speeds ranging be-
tween 50 and 200 MBaud. The transmit section accepts par-
allel data of selectable width and converts it to serial data,
while the receiver section accepts serial data and converts it
to parallel data of selectable width.
Figure 1
illustrates typical
connections between two independent host systems and cor-
responding CY7C954DX parts. As a second-generation
HOTLink device, the CY7C954DX provides enhanced levels of
Framer
Deserializer
Serializer
8B/10B
Encoder
FIFO
Receive
Data
Receive
System Host
Decoder
8B/10B
Serial Link
Transmit
FIFO
Transmit
Data
System Host
Control
CY7C954DX
Status
Serializer
Encoder
8B/10B
FIFO
Transmit
Data
Transmit
Serial Link
CY7C954DX
Deserializer
Framer
8B/10B
Decoder
Receive
FIFO
Control
Status
Receive
Data
Figure 1. HOTLink System Connections
HOTLink is a registered trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of International Business Machines.
Cypress Semiconductor Corporation
Document #: 38-02007 Rev. **
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised June 10, 2000
CY7C954DX
CY7C954DX Transceiver Logic Block Diagram
TX
STATUS
3
TXDATA
CONTROL
14
11
Mode
Control
TXCLK
MODE
REFCLK
6
4
11
RX
STATUS
RXDATA
RXCLK
CONTROL
ADDRSEL[2:0]
TXADDR[2:0]
RXADDR[2:0]
TXEN*
RXEN*
TXRST*
RXRST*
RFEN
TXBISTEN*
RXBISTEN*
RESET*
MODE
RANGESEL
SPDSEL
RXMODE[1:0]
EXTFIFO
TEST*
RXSTATUS
LFI*
RXEMPTY*
RXCLAV
RXFULL*
TX STATUS
TXEMPTY*
TXCLAV
TXFULL*
Output Register
Output Register
Input Register
Flags
Receive
FIFO
Flags
Transmit
FIFO
Transmit
PLL Clock
Multiplier
Elasticity
Buffer
MUX
Transmit
Formatter
Pipeline Register
HEC Generate
Receive
Control
State
Machine
Receive
Formatter
Pipeline Register
HEC Check
Cell Discard Policy
BIST LFSR
8B/10B Decoder
BIST LFSR
8B/10B Encoder
Transmit
Control
State
Machine
Deserializer
Framer
Clock
Divider
Serial Shifter
Bit Clock
Routing Matrix
Receive
Clock/Data
Recovery
Bit Clock
LOOPBACK
CONTROL
DLB[1:0]
LOOPTX
3
LOOPBACK
CONTROL
Document #: 38-02007 Rev. **
Signal
Validation
OUTA
INA
OUTB
CURSETB
CURSETA
INB
A/B*
CARDET
Page 2 of 43
CY7C954DX
Pin Configuration
RXBISTEN*
CURSETB
TQFP
Top View
CURSETA
CARDET
OUTB+
OUTB–
OUTA+
OUTA–
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
INA+
INB+
INA–
INB–
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TEST*
A/B*
LFI*
DLB[1]
DLB[0]
LOOPTX
TXBISTEN*
RXCLK
TXADDR[2]
RXFULL*
VSS
REFCLK
VSS
VDD
VSS
TXRST*
VDD
TXEN*
RXCLAV
TXSC/D*
RXEMPTY*
TXDATA[0]
RXSOC
RXMODE[1]
RXMODE[0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSSA
75
74
73
72
71
70
69
68
67
66
65
64
SPDSEL
RANGESEL
RFEN
TXFULL*
RXADDR[2]
TXCLAV
RXEN*
TXCLK
RXRST*
VSS
RXSC/D*
VDD
VSS
VDD
RXDATA[0]
TXEMPTY*
RXDATA[1]
TXSOC
VSS
TXSVS
VDD
TXADDR[1]
RXDATA[2]
RESET*
VSS
CY7C954DX
63
62
61
60
59
58
57
56
55
54
53
52
51
RXRVS
RXADDR[1]
RXADDR[0]
TXADDR[0]
TXDATA[1]
TXDATA[2]
RXDATA[7]
RXDATA[6]
RXDATA[5]
RXDATA[4]
ADDRSEL[1]
ADDRSEL[2]
RXDATA[3]
TXDATA[3]
TXDATA[4]
TXDATA[6]
TXDATA[5]
TXDATA[7]
EXTFIFO
VSS
VSS
VSS
VSS
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +6.5V
DC Voltage Applied to Outputs
in High-Z State .........................................–0.5V to V
DD
+0.5V
Output Current into TTL Outputs (LOW)......................30 mA
DC Input Voltage ..................................... –0.5V to V
DD
+0.5V
Static Discharge Voltage ......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
5.0V
±
10%
Document #: 38-02007 Rev. **
ADDRSEL[0]
VDD
Page 3 of 43
CY7C954DX
Pin Descriptions
Pin #
Name
I/O Characteristics
TTL input, sampled
on TXCLK↑,
Internal Pull-Up
TTL input, sampled
on TXCLK↑,
Internal Pull-Up
TTL input, sampled
on TXCLK↑,
Internal Pull-Up
TTL input, sampled
on TXCLK↑,
Internal Pull-Up
TTL input, sampled
on TXCLK↑,
Internal Pull-Up
TTL input, sampled
on TXCLK↑,
Internal Pull-Up on
TTL clock input,
Internal Pull-Up
3-state TTL output,
changes following
TXCLK↑
Parallel Transmit Data Input.
These inputs contain data that is written to the Transmitter FIFO when
TXADDR[2:0] matches ADDRSEL[2:0] and transmitter input is selected by
TXEN*.
Transmit Send Violation Symbol Input.
This input is interpreted along with TXSOC and TXSC/D* (see
Table 1
for
details).
Transmit Start of Cell Input.
This input is used as a message frame delimiter to indicate the beginning of a
data packet. It is interpreted along with TXSVS and TXSC/D* (see
Table 1
for
details).
Transmit Special Character or Data Select Input.
This input is interpreted along with TXSVS and TXSOC (see
Table 1
for de-
tails).
Transmit Enable Input.
Data enable for the TXDATA bus write operations. Active LOW when config-
ured for UTOPIA timing, active HIGH when configured for Cascade timing.
Transmit Address Select Input.
This is the three bit Transmit Port address that is matched to ADDRSEL[2:0]
to enable data transfer from the transmitting system.
Transmit FIFO Clock.
The input clock for the transmit parallel interface. Used to sample all Transmit
FIFO related interface signals.
Transmit FIFO Full Status Flag.
Active LOW when configured for UTOPIA timing, active HIGH when configured
for Cascade timing. When TXFULL* is first asserted, the Transmit FIFO can
still accept a minimum of four write cycles without loss of data. FIFO flags are
updated one TXCLK cycle after an address match condition exists.
Transmit FIFO Cell Available Status Flag. Active LOW.
TXCLAV is asserted LOW when the Transmit FIFO has sufficient space to
insert one or more 53-byte ATM cells.
TXCLAV is forced to the High-Z state only during a “full-chip” reset (i.e., while
RESET* is LOW) or on the cycle after an “unmatch” in TXADDR[2:0]. (Used
for polling FIFO status.)
FIFO flags are updated one TXCLK cycle after an address match condition
exists.
60
TXEMPTY*
3-state TTL output,
changes following
TXCLK↑
Transmit FIFO Empty Status Flag.
Active LOW when configured for UTOPIA timing, active HIGH when configured
for Cascade timing.
TXEMPTY* is asserted either when no data has been loaded into the Transmit
FIFO, or when the Transmit FIFO has been emptied by either a Transmit FIFO
reset or by the normal transmission of the FIFO contents.
When TXBISTEN* is asserted LOW, TXEMPTY* becomes the transmit BIST-
loop counter indicator. In this mode TXEMPTY* is asserted for one TXCLK
period at the end of each transmitted BIST sequence.
FIFO flags are updated one TXCLK cycle after an address match condition
exists.
Signal Description
Transmit Path Signals
44, 42, TXDATA[7:0]
40, 36,
34, 32,
30, 22
56
TXSVS
58
TXSOC
20
TXSC/D*
18
TXEN*
9, 54,
46
68
TXADDR[2:0]
TXCLK
72
TXFULL*
70
TXCLAV
3-state TTL output,
changes following
TXCLK↑
Document #: 38-02007 Rev. **
Page 4 of 43
CY7C954DX
Pin Descriptions
(continued)
Pin #
16
Name
TXRST*
I/O Characteristics
TTL input, internal
pull-up, sampled on
TXCLK↑,
Internal Pull-Up
TTL input,
asynchronous,
Internal Pull-Up
Transmit FIFO Reset.
When TXRST* is sampled asserted (LOW) for eight or more TXCLK cycles, a
reset operation is started on the Transmit FIFO.
Transmitter BIST Enable.
When TXBISTEN* is LOW, the transmitter generates a 511-character repeat-
ing sequence, that can be used to validate link integrity. The transmitter returns
to normal operation when TXBISTEN* is HIGH. All Transmit FIFO read oper-
ations are suspended when BIST is active.
Parallel Data Output.
These outputs change following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Received Violation Symbol Indicator.
In Receive mode (11), this output is the indicator that data has been received
continuing errors, and is decoded in conjunction with RXSC/D* and RXSOC,
per
Table 4,
to indicate the presence of specific Special Character codes in the
received data stream.
This output is unused for the other receive modes, except that RXRVS is used
to report character mismatches when RXBISTEN* is LOW
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
23
RXSOC
3-state TTL output,
changes following
RXCLK↑
Receive Start Of Cell.
This output is one of the indicators for the start of a cell and is decoded in
conjunction with RXSC/D* and RXRVS, per
Table 4,
to indicate the presence
of specific Special Character codes in the received data stream.
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
65
RXSC/D*
3-state TTL output,
changes following
RXCLK↑
Received Special Character or Data Indicator.
This signal is use to differentiate between Special Characters and Data bytes.
It is also decoded in conjunction with RXSOC and RXRVS, per
Table 4,
to
indicate the presence of specific Special Character codes in the received data
stream.
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
69
RXEN*
TTL input, sampled
on RXCLK↑,
Internal Pull-Up
TTL input, sampled
on RXCLK↑
TTL output clock,
Internal Pull-Up
Receive Enable.
Data enable for the RXDATA bus write and read operations. Active LOW when
configured for UTOPIA timing, active HIGH when configured for Cascade tim-
ing as determined by the EXTFIFO pin.
Receive Address Input.
This is the three-bit Receive Port address that is matched to ADDRSEL[2:0] to
enable data transfer to the receiving system.
Receive Clock.
This clock is the Receive interface input clock and is used to control Receive
FIFO read, reset, and serial register access operations.
Signal Description
7
TXBISTEN*
Receive Path Signals
41, 43, RXDATA[7:0]
45, 47,
48, 53,
59, 61
29
RXRVS
3-state TTL output,
changes following
RXCLK↑
3-state TTL output,
changes following
RXCLK↑,
Internal Pull-Up
71,31,
33
8
RXADDR[2:0]
RXCLK
Document #: 38-02007 Rev. **
Page 5 of 43
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