P4080V3MMB datasheet, PDF - EEWORLD Datasheet

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P4080V3MMB: DescriptionMicroprocessor, 1200MHz, CMOS, PBGA1295, 37.50 X 37.50 MM, 1 MM PITCH, 3.53 MM HEIGHT, PLASTIC, FCBGA-1295; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，150 Pages; Manufacturere2v technologies

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P4080V3MMB Overview

Microprocessor, 1200MHz, CMOS, PBGA1295, 37.50 X 37.50 MM, 1 MM PITCH, 3.53 MM HEIGHT, PLASTIC, FCBGA-1295

P4080V3MMB Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA,
Contacts	1295
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	16
boundary scan	YES
maximum clock frequency	133.3 MHz
External data bus width	16
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B1295
length	37.5 mm
low power mode	NO
Number of terminals	1295
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.53 mm
speed	1200 MHz
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	37.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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P4080

QorIQ Integrated Processor

Hardware Specifications

Datasheet

The P4080 QorIQ integrated communication processor combines eight Power Architecture

processor cores with high

performance data path acceleration logic and network and peripheral bus interfaces required for power intensive

applications in aerospace, defence and demanding outdoor environments.

This device can be used for combined control, data path, and application layer processing. Its high level of integration

offers significant performance benefits compared to multiple discrete devices, while also greatly simplifying board design.

The device SoC includes the following function and features:

•

Eight e500-mc Power Architecture Cores, Each with a Backside 128-Kbyte

L2 Cache with ECC

– Three Levels of instructions: User, Supervisor, and Hypervisor

– Independent Boot and Reset

– Secure Boot Capability

CoreNet Fabric Supporting Coherent and non-coherent Transactions

Amongst CoreNet End-points

A Frontside 2-Mbyte L3 Cache with ECC

CoreNet Bridges Between the CoreNet Fabric the I/Os, Data Path

Accelerators, and High and Low

Speed Peripheral Interfaces

Two 10-Gigabit Ethernet (XAUI) Controllers

Eight 1-Gigabit Ethernet Controllers

Two 64-bit DDR2/DDR3 SDRAM Memory Controllers with ECC

Multicore Programmable Interrupt Controller

Four I

C Controllers

Four 2-pin UARTs or two 4-pin UARTs

Two 4-channel DMA Engines

Enhanced Local Bus Controller (eLBC)

Three PCI Express 2.0 Controllers/Ports

Two Serial RapidIO

1.2 Controllers/Ports

Enhanced Secure Digital Host Controller (SD/MMC)

Enhanced Serial Peripheral Interfaces (eSPI)

High-speed USB Controller (USB 2.0)

– Host and Device Support

– Enhanced Host Controller Interface (EHCI)

– ULPI Interface to PHY

•

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2011

1066A–HIREL–07/11

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